Patents by Inventor Guobiao Zhang

Guobiao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configurable computing array for implementing complex math functions
    Patent number: 10312917
    Abstract: To implement a complex math function, a configurable computing array comprises at least an array of configurable interconnects, an array of configurable logic elements and an array of configurable computing elements. Each configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 4, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Vertically Integrated Neuro-Processor
    Publication number: 20190164038
    Abstract: A vertically integrated neuro-processor comprises a plurality of neural storage-processing units (NSPU's). Each NSPU comprises at least a neuro-storage circuit and a neuro-processing circuit. The neuro-storage circuit comprises a memory array for storing at least a synaptic weight, while the neuro-processing circuit performs neural processing with the synaptic weight. The memory array and the neuro-processing circuit are vertically stacked and communicatively coupled by a plurality of inter-level connections.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 30, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Compact three-dimensional memory with semi-conductive address line portion
    Patent number: 10304495
    Abstract: In a compact three-dimensional memory (3D-MC), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 28, 2019
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Configurable computing array package based on printed memory
    Patent number: 10305486
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array package. It comprises at least a configurable computing die and a configurable logic die. The configurable computing die comprises at least one configurable computing element. The configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions. The configurable computing die and the configurable logic die are located in a same package.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Compact three-dimensional memory with an above-substrate decoding stage
    Patent number: 10304553
    Abstract: The above-substrate decoding stage of a compact three-dimensional memory (3D-Mc) could be an intra-level decoding stage, an inter-level decoding stage, or a combination thereof. For the intra-level decoding stage, contact vias can be shared by address-lines in the same memory level; for the inter-level decoding stage, contact vias can be shared by address-lines from different memory levels.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 28, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Monolithic Three-Dimensional Pattern Processor
    Publication number: 20190158510
    Abstract: A monolithic three-dimensional (3-D) pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a 3-D memory (3D-M) array and a pattern-processing circuit. The 3D-M could be a horizontal 3D-M (3D-MH) or a vertical 3D-M (3D-MV). The 3D-M array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of intra-die connections.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 23, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Computing Array
    Publication number: 20190158095
    Abstract: A configurable computing array comprises at least an array of configurable interconnects, at least an array of configurable logic elements and at least an array of configurable computing elements. Each configurable computing element comprises at least a programmable memory for storing a look-up table (LUT) for a math function.
    Type: Application
    Filed: November 11, 2018
    Publication date: May 23, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Processor For Implementing Mathematical Functions or Models
    Publication number: 20190115922
    Abstract: A processor comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and at least one three-dimensional memory (3D-M) array. The 3D-M array stores at least a portion of a look-up table (LUT) for a non-arithmetic function, while the ALC performs arithmetic operations on the LUT data.
    Type: Application
    Filed: November 26, 2018
    Publication date: April 18, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Chen SHEN
  • Configurable Processor with Backside Look-Up Table
    Publication number: 20190114139
    Abstract: A configurable processor comprises a processor substrate with a front side and a backside. A programmable memory array is disposed on the backside for storing a look-up table (LUT) for a mathematical function, while an arithmetic logic circuit (ALC) is disposed on the front side for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 18, 2019
    Inventor: Guobiao ZHANG
  • Configurable Computing-Array Package
    Publication number: 20190115921
    Abstract: A configurable computing-array package comprises a configurable computing die including an array of configurable computing elements and a configurable logic die including an array of configurable logic elements. Each configurable computing element stores a look-up table (LUT) for a non-arithmetic function, i.e. a math function whose operations involve more than addition and subtraction. The configurable computing-array package can be configured to realize different complex math functions.
    Type: Application
    Filed: November 24, 2018
    Publication date: April 18, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Computing-Array Package Implementing Complex Math Functions
    Publication number: 20190115920
    Abstract: A preferred configurable computing-array package comprises a configurable logic die including an array of configurable logic elements and a configurable computing die including an array of configurable computing elements. Each configurable logic element is capable of realizing any one of a plurality of logic functions in a logic library. Each configurable computing element stores at least a look-up table (LUT) for a math function, which includes more operations than the arithmetic operations included in the logic library.
    Type: Application
    Filed: November 25, 2018
    Publication date: April 18, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable Processor with In-Package Look-Up Table
    Publication number: 20190114138
    Abstract: A configurable processor comprises a memory die and a logic die. The memory die comprises a programmable memory array for storing a look-up table (LUT) for a mathematical function, while the logic die comprises an arithmetic logic circuit (ALC) for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 18, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Processor for Implementing Non-Arithmetic Functions
    Publication number: 20190115923
    Abstract: A processor comprises an array of computing elements, with each computing element comprising an arithmetic logic circuit (ALC) and at least one three-dimensional memory (3D-M) array. The 3D-M array stores at least a portion of a look-up table (LUT) for a non-arithmetic function, while the ALC performs arithmetic operations on the LUT data. Because they include more operations than the basic arithmetic operations (i.e. addition, subtraction and multiplication), the non-arithmetic functions cannot be implemented by the conventional logic circuits alone.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 18, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Chen SHEN
  • Processor Using Memory-Based Computation
    Publication number: 20190114170
    Abstract: Instead of logic-based computation (LBC), the preferred processor disclosed in the present invention uses memory-based computation (MBC). It comprises an array of computing elements, with each computing element comprising a memory array on a memory level for storing a look-up table (LUT) and an arithmetic logic circuit (ALC) on a logic level for performing arithmetic operations on selected LUT data. The memory level and the logic level are different physical levels.
    Type: Application
    Filed: November 12, 2018
    Publication date: April 18, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable gate array comprising three-dimensional printed memory
    Patent number: 10230375
    Abstract: The present invention discloses a configurable gate array comprising three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 12, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Configurable computing array based on three-dimensional printed memory
    Patent number: 10211836
    Abstract: The present invention discloses a configurable computing array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 19, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Manufacturing methods of JFET-type compact three-dimensional memory
    Patent number: 10211258
    Abstract: Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: February 19, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Manufacturing methods of MOSFET-type compact three-dimensional memory
    Patent number: 10199432
    Abstract: Manufacturing methods of MOSFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A MOSFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 5, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Positioning Method Using Broadcast Speeches
    Publication number: 20180364050
    Abstract: A positioning method using music pieces continuously provides positioning service. At each signature burst (i.e., a highly unique short musical segment suitable for positioning), sounds of a music piece are used for positioning. Between signature bursts, dead reckoning (DR) is used.
    Type: Application
    Filed: August 7, 2018
    Publication date: December 20, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Double-Biased Three-Dimensional One-Time-Programmable Memory
    Publication number: 20180366207
    Abstract: To reduce the pre-programming cost, a double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. The OTP array comprises a dummy word line and a plurality of data word lines. During read, both voltages on the dummy word line and a selected data word line are raised.
    Type: Application
    Filed: September 9, 2018
    Publication date: December 20, 2018
    Applicant: ChengDu SanWei IP Technology LLC
    Inventor: Guobiao ZHANG