Patents by Inventor Guobiao Zhang

Guobiao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180261226
    Abstract: A preferred speech-recognition processor performs pattern processing (i.e. pattern recognition) between an acoustic/language model and an audio data. It comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The plurality of SPUs can perform pattern processing simultaneously.
    Type: Application
    Filed: May 8, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Publication number: 20180260477
    Abstract: A preferred audio storage with in-situ audio-searching capabilities not only stores audio data, but also performs pattern recognition thereto. It comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The 3D-M array stores at least a portion of audio data, while the input includes at least a portion of an audio pattern.
    Type: Application
    Filed: May 8, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Publication number: 20180260344
    Abstract: The present invention discloses a distributed pattern storage-processing circuit. It not only stores patterns permanently, but also processes them with massive parallelism. The preferred pattern storage-processing circuit comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The plurality of SPUs performs pattern processing simultaneously.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Publication number: 20180260644
    Abstract: A preferred data storage with in-situ string-searching capabilities comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional vertical memory (3D-MV) array vertically stacked above a pattern-processing circuit. The 3D-MV array stores at least a portion of big data. A search string from the input is sent to all SPUs, which perform string searching simultaneously.
    Type: Application
    Filed: May 9, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Publication number: 20180260449
    Abstract: A distributed pattern storage-processing circuit not only stores patterns permanently, but also processes them with massive parallelism. It comprises a plurality of storage-processing units (SPU), with each SPU comprising at least a three-dimensional memory (3D-M) array vertically stacked above a pattern-processing circuit. The plurality of SPUs performs pattern processing simultaneously.
    Type: Application
    Filed: May 8, 2018
    Publication date: September 13, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Patent number: 10075590
    Abstract: To detect side-by-side parked vehicles at night, the present invention discloses a night-detection device and method. The night-detection device comprises a moving-vehicle sensor and a parked-vehicle sensor. It uses the light beam from a passing-by vehicle to extract at least a reflection of at least a head-light or at least a portion of a front bumper.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 11, 2018
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 10075169
    Abstract: The present invention discloses a configurable computing array. It is a monolithic integrated circuit comprising at least a configurable computing element and a configurable logic element. The configurable computing element comprises at least a three-dimensional vertical writable memory (3D-WV) array, which is stacked above the configurable logic element and stores at least a portion of a look-up table (LUT) for a math function.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 11, 2018
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 10075168
    Abstract: The present invention discloses a configurable computing array comprising three-dimensional writable memory (3D-W). It is a monolithic integrated circuit comprising an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which stores at least a portion of a look-up table (LUT) for a math function.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 11, 2018
    Assignees: XiaMen HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Publication number: 20180226414
    Abstract: The present invention discloses a three-dimensional vertical read-only memory (3D-OTPV) comprising Schottky diodes. It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. A plurality of Schottky diodes are formed between the horizontal address lines and the vertical address lines.
    Type: Application
    Filed: April 8, 2018
    Publication date: August 9, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20180212606
    Abstract: The present invention discloses a configurable computing array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20180204845
    Abstract: The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTPV). It comprises horizontal address lines and memory holes there-through, a re-programmable layer and vertical address lines in said memory holes. The re-programmable layer comprises at least first and second sub-layers with different re-programmable materials. The 3D-MTPV comprises no separate diode layer.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Publication number: 20180204844
    Abstract: The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises horizontal address lines and memory holes there-through, an antifuse layer and vertical address lines in said memory holes. The antifuse layer comprises at least first and second sub-layers with different antifuse materials. The 3D-OTPV comprises no separate diode layer.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Inventor: Guobiao ZHANG
  • Publication number: 20180205380
    Abstract: The present invention discloses a configurable gate array comprising three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20180198448
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array die based on two-sided integration. It is a monolithic die and comprises at least a configurable computing element and a configurable logic element formed on different sides of a semiconductor substrate. Each configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Publication number: 20180198449
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array package. It comprises at least a configurable computing die and a configurable logic die. The configurable computing die comprises at least one configurable computing element. The configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions. The configurable computing die and the configurable logic die are located in a same package.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Publication number: 20180189586
    Abstract: The present invention discloses a three-dimensional memory (3D-M) with in-situ string-searching capabilities (3D-MSS). It comprises a plurality of storage-processing units (SPU). Each SPU comprises at least a 3D-M array for storing computer data and a pattern-processing circuit for searching the computer data for a search string. The 3D-M array is stacked above the pattern-processing circuit. Multiple 3D-MSS dice can form a storage card or a solid-state drive with in-situ string-searching capabilities.
    Type: Application
    Filed: October 13, 2017
    Publication date: July 5, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20180190715
    Abstract: The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTPV) with a thin memory layer. It comprises a plurality of vertically stacked horizontal address lines, at least a memory hole through the horizontal address lines, a memory layer and a vertical address line disposed in the memory hole. Because the thickness of the memory layer is less than 100 nm, the MTP cell is leaky. Sense amplifiers and a full-read mode are used to ensure a properly working 3D-MTPV.
    Type: Application
    Filed: March 3, 2018
    Publication date: July 5, 2018
    Inventor: Guobiao ZHANG
  • Publication number: 20180190716
    Abstract: The present invention discloses a three-dimensional vertical multiple-time-programmable memory (3D-MTPV) comprising no separate diode layer. It comprises a plurality of vertically stacked horizontal address lines, at least a memory hole through the horizontal address lines, a memory layer and a vertical address line disposed in the memory hole. The memory layer comprises a re-programmable layer but no separate diode layer. The memory layer is leaky, i.e. its reverse current is comparable to its forward current. Sense amplifiers and a full-read mode are used to ensure a properly working 3D-MTPV.
    Type: Application
    Filed: March 3, 2018
    Publication date: July 5, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20180189585
    Abstract: The present invention discloses a three-dimensional memory (3D-M) with in-situ anti-malware capabilities (3D-MAM). It comprises a plurality of storage-processing units (SPU). Each SPU comprises at least a 3D-M array for storing computer data and a pattern-processing circuit for screening the computer data against a malware pattern. The 3D-M array is stacked above the pattern-processing circuit. Multiple 3D-MAM dice can form a storage card, or a solid-state drive with in-situ anti-malware capabilities.
    Type: Application
    Filed: October 13, 2017
    Publication date: July 5, 2018
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Patent number: 10002872
    Abstract: The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The horizontal address lines and the vertical address lines comprise oppositely-doped semiconductor materials.
    Type: Grant
    Filed: April 16, 2017
    Date of Patent: June 19, 2018
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang