Patents by Inventor Guobiao Zhang

Guobiao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three-dimensional vertical one-time-programmable memory comprising multiple antifuse sub-layers
    Patent number: 10490562
    Abstract: The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises horizontal address lines and memory holes there-through, an antifuse layer and vertical address lines in said memory holes. The antifuse layer comprises at least first and second sub-layers with different antifuse materials. The 3D-OTPV comprises no separate diode layer.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: November 26, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Processor for enhancing computer security
    Patent number: 10489590
    Abstract: The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: November 26, 2019
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Night detection of front-parked vehicles
    Patent number: 10464479
    Abstract: To detect front-parked vehicles at night (i.e. a vehicle is parked with its head facing the inside of a parking space), the present invention discloses a night-detection device. It comprises a moving-vehicle sensor and a parked-vehicle sensor. It uses the light beam from a passing-by vehicle to extract at least a reflection of at least a tail light or at least a portion of a back bumper.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: November 5, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Configurable computing array comprising configurable computing elements
    Patent number: 10456800
    Abstract: To implement a complex math function, i.e. a math function with multiple input variables, a configurable computing array comprises at least an array of configurable computing elements. Each configurable computing element comprises at least a memory which stores a look-up table (LUT) for a math function with a single input variable.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: October 29, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Processor for Calculating Mathematical Functions in Parallel
    Publication number: 20190324942
    Abstract: A three-dimensional processor (3D-processor) for calculating mathematical functions in parallel, comprises a larger number (e.g. at least one thousand) of computing elements, with each computing element comprising at least one three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Even though each individual 3D-M cell is slower than a conventional two-dimensional memory (2D-M) cell, this deficiency in speed is offset by a significantly larger scale of parallelism.
    Type: Application
    Filed: June 30, 2019
    Publication date: October 24, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Chen SHEN
  • Monolithic Three-Dimensional Pattern Processor Comprising Many Storage-Processing Units
    Publication number: 20190327247
    Abstract: A monolithic three-dimensional (3-D) pattern processor comprises at least one thousand storage-processing units (SPU's). Each SPU comprises at least a 3-D memory (3D-M) array and a pattern-processing circuit, with the 3D-M array vertically stacked above the pattern-processing circuit. The preferred pattern processor supports massive parallelism.
    Type: Application
    Filed: June 8, 2019
    Publication date: October 24, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Shared bicycle comprising an infrared sensor
    Patent number: 10444370
    Abstract: A preferred IR-bicycle comprises an infrared (IR) sensor and non-IR electronics. The IR sensor detects a person in the proximity of the IR-bicycle (i.e. a nearby person). Once the IR sensor detects a nearby person, the non-IR electronics switches from a first mode to a second mode, wherein the power consumption in the first mode is substantially lower than that in the second mode.
    Type: Grant
    Filed: April 29, 2018
    Date of Patent: October 15, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao Zhang, Chuan Tang
  • Configurable processor with in-package look-up table
    Patent number: 10445067
    Abstract: A configurable processor comprises a memory die and a logic die. The memory die comprises a programmable memory array for storing a look-up table (LUT) for a mathematical function, while the logic die comprises an arithmetic logic circuit (ALC) for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: October 15, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Coordinated parking-monitoring system
    Patent number: 10446030
    Abstract: The present invention discloses a coordinated parking-monitoring system. A co-monitored parking space is monitored by at least two parking-monitoring devices. Its effective parking-monitoring area is substantially more than that if it were monitored by a single parking-monitoring device. This lowers the overall system cost.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 15, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: WenSheng Wang, Guobiao Zhang
  • Mixed three-dimensional memory
    Patent number: 10446193
    Abstract: The present invention discloses a mixed three-dimensional memory (3D-Mx). It comprises memory arrays (or, memory blocks) of different sizes. In a 3D-Mx with mixed memory blocks, the memory blocks with different sizes are formed side-by-side. In a 3D-Mx with mixed memory arrays, a plurality of small memory arrays are formed side-by-side underneath a single large memory array.
    Type: Grant
    Filed: April 23, 2017
    Date of Patent: October 15, 2019
    Assignees: Hangzhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • COORDINATED PARKING-MONITORING SYSTEM
    Publication number: 20190311624
    Abstract: The present invention discloses a coordinated parking-monitoring system. A co-monitored parking space is monitored by at least two parking-monitoring devices. Its effective parking-monitoring area is substantially more than that if it were monitored by a single parking-monitoring device. This lowers the overall system cost.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: WenSheng WANG, Guobiao ZHANG
  • Processor for realizing at least two categories of functions
    Patent number: 10372359
    Abstract: The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 6, 2019
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Monolithic Three-Dimensional Pattern Processor Supporting Massive Parallelism
    Publication number: 20190230096
    Abstract: A monolithic three-dimensional (3-D) pattern processor supporting massive parallelism comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a 3-D memory (3D-M) array and a pattern-processing circuit. Being monolithic, the 3D-M arrays and the pattern-processing circuits of the preferred pattern processor are formed on a single die and communicatively coupled by a plurality of intra-die connections. To ensure parallelism, each of the SPU's comprises no more than eight 3D-M arrays.
    Type: Application
    Filed: March 31, 2019
    Publication date: July 25, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Distributed Pattern Processor Package
    Publication number: 20190220680
    Abstract: A distributed pattern processor package comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a non-volatile memory (NVM) array and a pattern-processing circuit. The preferred processor package further comprises at least a memory die and a logic die. The NVM arrays are disposed on the memory die, whereas the pattern-processing circuits are disposed on the logic die. The memory and logic dice are communicatively coupled by a plurality of inter-die connections.
    Type: Application
    Filed: January 27, 2019
    Publication date: July 18, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Hetero-Epitaxial Output Device Array
    Publication number: 20190198624
    Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. The substrate surface has multiple grids, upon which multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. By disabling defective transistors, the overall yield/reliability is improved.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 27, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Peter Y. YU
  • Bi-Sided Pattern Processor
    Publication number: 20190180815
    Abstract: A bi-sided pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a memory array and a pattern-processing circuit. The preferred pattern processor further comprises a semiconductor substrate with opposing first and second surfaces. The memory array is disposed on the first surface, whereas the pattern-processing circuit is disposed on the second surface. The memory array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of inter-surface connections.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 13, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Multi-Level Distributed Pattern Processor
    Publication number: 20190171815
    Abstract: A multi-level distributed pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a non-volatile memory (NVM) array and a pattern-processing circuit. The NVM array and the pattern-processing circuit are disposed on different physical levels.
    Type: Application
    Filed: January 27, 2019
    Publication date: June 6, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable computing array for implementing complex math functions
    Patent number: 10312917
    Abstract: To implement a complex math function, a configurable computing array comprises at least an array of configurable interconnects, an array of configurable logic elements and an array of configurable computing elements. Each configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 4, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Vertically Integrated Neuro-Processor
    Publication number: 20190164038
    Abstract: A vertically integrated neuro-processor comprises a plurality of neural storage-processing units (NSPU's). Each NSPU comprises at least a neuro-storage circuit and a neuro-processing circuit. The neuro-storage circuit comprises a memory array for storing at least a synaptic weight, while the neuro-processing circuit performs neural processing with the synaptic weight. The memory array and the neuro-processing circuit are vertically stacked and communicatively coupled by a plurality of inter-level connections.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 30, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao ZHANG
  • Configurable computing array package based on printed memory
    Patent number: 10305486
    Abstract: The present invention discloses a new type of configurable gate array—a configurable computing array package. It comprises at least a configurable computing die and a configurable logic die. The configurable computing die comprises at least one configurable computing element. The configurable computing element can selectively realize a basic function from a math library. It comprises a plurality of printed arrays for storing the look-up tables (LUT) for different basic functions. The configurable computing die and the configurable logic die are located in a same package.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang