Patents by Inventor Guoqing Zhang

Guoqing Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190002501
    Abstract: The invention provides processes of purifying a peptide including a GCC agonist sequence selected from the group consisting of SEQ ID NOs: 1-251 described herein. The processes include a solvent exchange step before a freeze-drying (lyophilization) step.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 3, 2019
    Inventors: Kunwar Shailubhai, Stephen Comiskey, Rong Feng, Juncai Bai, Ruoping Zhang, Jun Jia, Junfeng Zhou, Qiao Zhao, Guoqing Zhang
  • Patent number: 10090009
    Abstract: An apparatus includes a disk locked clock system and a feedforward microactuator compensator. The disk locked clock system is configured to estimate a timing error and generate a timing error signal. The feedforward microactuator compensator is configured to generate a microactuator compensation signal, without use of a vibration sensor signal, in response to the timing error signal.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 2, 2018
    Assignee: Seagate Technology LLC
    Inventors: Qiang Bi, GuoQing Zhang, Kian Keong Ooi, MingZhong Ding, WenJun Cao
  • Patent number: 10090831
    Abstract: The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A?40) to (A?8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A?80) to (A?16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd?Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: October 2, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Jun Wang, Xinxin Jin, Liang Sun, Yuebai Han, Guoqing Zhang
  • Patent number: 10051670
    Abstract: Human proximity detection techniques for wireless communication devices are described. In one embodiment, for example, an apparatus may comprise a memory and logic, at least a portion of the logic comprised in circuitry coupled to the memory, the logic to perform a connection establishment procedure to establish a wireless link with a human proximity reporting (HPR) device, identify heart rate information comprised in a human proximity report received from the HPR device via the wireless link, determine an initial HPR state based on the heart rate information, and select an initial operating mode for a feature of a human proximity monitoring (HPM) device based on the initial HPR state. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: August 14, 2018
    Assignee: INTEL CORPORATION
    Inventor: Guoqing Zhang
  • Publication number: 20180188289
    Abstract: A display substrate includes: a display driving signal line; and at least one set of testing pads, wherein each set of the testing pads includes: a plurality of light-on testing pads arranged successively and connected to the display driving signal line; and two pin-miss testing pads electrically connected to one another while not connected to the display driving signal line.
    Type: Application
    Filed: May 13, 2016
    Publication date: July 5, 2018
    Applicants: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Yi Qu, Guoqing Zhang, Zhigang Sun, Hongxia Yang, Shanshan Bao, Jun Wang, Tuan Liang
  • Patent number: 10011637
    Abstract: The invention provides processes of purifying a peptide including a GCC agonist sequence selected from the group consisting of SEQ ID NOs: 1-251 described herein. The processes include a solvent exchange step before a freeze-drying (lyophilization) step.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: July 3, 2018
    Assignee: SYNERGY PHARMACEUTICALS, INC.
    Inventors: Kunwar Shailubhai, Stephen Comiskey, Rong Feng, Juncai Bai, Ruoping Zhang, Jun Jia, Junfeng Zhou, Qiao Zhao, Guoqing Zhang
  • Patent number: 10002630
    Abstract: An apparatus includes a frequency analyzer circuitry, filter circuitry, and voice coil motor (VCM) control circuitry. The frequency analyzer circuitry is configured to detect one or more dominant frequencies of a position error signal (PES). The filter circuitry is configured to identify one or more filters in response to detecting the one or more dominant frequencies, apply the one or more identified filters to at least one of a microactuator control signal and PES, and generate a VCM compensation signal in response to the filtered PES or the microactuator control signal. The VCM control circuitry is configured to generate a VCM control signal in response to the VCM compensation signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 19, 2018
    Assignee: Seagate Technology LLC
    Inventors: Hoang Dung Vu, Xiang Lu, GuoQing Zhang, Chan Fan Lau
  • Publication number: 20180061452
    Abstract: An apparatus includes a disk locked clock system and a feedforward microactuator compensator. The disk locked clock system is configured to estimate a timing error and generate a timing error signal. The feedforward microactuator compensator is configured to generate a microactuator compensation signal, without use of a vibration sensor signal, in response to the timing error signal.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Inventors: Qiang Bi, GuoQing Zhang, Kian Keong Ooi, MingZhong Ding, WenJun Cao
  • Patent number: 9858955
    Abstract: An apparatus includes a microactuator controller configured to generate a microactuator control signal, a feedforward microactuator compensator configured to generate a microactuator compensation signal, and a microactuator model filter configured to filter a modified microactuator control signal. The microactuator compensation signal is configured to be injected into the microactuator control signal to generate the modified microactuator control signal. The microactuator model filter generates a filtered modified microactuator control signal and injects the filtered modified microactuator control signal into a position error signal to generate a modified position error signal.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: January 2, 2018
    Assignee: Seagate Technology LLC
    Inventors: WenJun Cao, GuoQing Zhang, Xiang Lu, Qiang Bi, MingZhong Ding, Lou Supino
  • Patent number: 9795928
    Abstract: Novel low-pressure nanofiltration membrane composites for rejecting organic compounds are prepared by interfacial polymerization on a microporous hollow fiber supporting membrane. The interfacial polymerization reaction is carried out using an essentially monomeric polyamine reactant having at least two amine functional groups per molecule, and an essentially monomeric amine-reactive polyfunctional aromatic or cycloaliphatic acyl halide having at least two acyl halide groups per molecule. The composite can be fabricated by stepwise polymerization reactions with different reactant recipes at each step.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: October 24, 2017
    Assignee: Nano and Advanced Materials Institute Limited
    Inventors: Kaimin Shih, Guoqing Zhang
  • Publication number: 20170302265
    Abstract: The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A-40) to (A-8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A-80) to (A-16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd?Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.
    Type: Application
    Filed: April 9, 2015
    Publication date: October 19, 2017
    Inventors: Jun WANG, Xinxin JIN, Liang SUN, Yuebai HAN, Guoqing ZHANG
  • Publication number: 20170290070
    Abstract: Human proximity detection techniques for wireless communication devices are described. In one embodiment, for example, an apparatus may comprise a memory and logic, at least a portion of the logic comprised in circuitry coupled to the memory, the logic to perform a connection establishment procedure to establish a wireless link with a human proximity reporting (HPR) device, identify heart rate information comprised in a human proximity report received from the HPR device via the wireless link, determine an initial HPR state based on the heart rate information, and select an initial operating mode for a feature of a human proximity monitoring (HPM) device based on the initial HPR state. Other embodiments are described and claimed.
    Type: Application
    Filed: April 2, 2016
    Publication date: October 5, 2017
    Applicant: INTEL CORPORATION
    Inventor: GUOQING ZHANG
  • Patent number: 9710581
    Abstract: Using verification IP (VIP), the related design IP (DIP) can be integrated into a system on a chip (SOC) without requiring the IP component. Using a normalized framework, a software module can be integrated into the VIP software stack enabling the customized management of the VIP beyond the standard specification defined behaviors. Then, the modified software stack can be used to manage both behaviors defined by the specification and the design specific behaviors. The VIP can then be used in place of the DIP for SOC development.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 18, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Erik S. Panu
  • Publication number: 20170029467
    Abstract: The present disclosure provides a method of producing bivalirudin using a peptide fragment or peptide fragments on solid phase peptide synthesis that minimizes, or eliminates, the production of bivalirudin molecules having too few or too many glycine residues.
    Type: Application
    Filed: May 31, 2016
    Publication date: February 2, 2017
    Inventors: Guoqing Zhang, Ruoping Zhang, Juncai Bai
  • Publication number: 20160145307
    Abstract: The invention provides processes of purifying a peptide including a GCC agonist sequence selected from the group consisting of SEQ ID NOs: 1-251 described herein. The processes include a solvent exchange step before a freeze-drying (lyophilization) step.
    Type: Application
    Filed: June 5, 2014
    Publication date: May 26, 2016
    Inventors: Kunwar SHAILUBHAI, Stephen COMISKEY, Rong FENG, Juncai BAI, Ruoping ZHANG, Jun JIA, Junfeng ZHOU, Qiao ZHAO, Guoqing ZHANG
  • Patent number: 9280627
    Abstract: A system and method that implement an object-oriented model for requirements of a hardware design in order to verify the design. The object-oriented model abstractly captures the design topology, capability, control, and status of the design. An object-oriented model or definition of a hardware design is based on one or more specifications or standards implemented with the design. With the object-oriented model, a system and method for storing and displaying data captured during a test run is implemented. Graphical displays are defined to show run information for abstract objects of the design. Predefined graphical displays may be altered to accommodate the features of the object-oriented model and new graphical displays may be defined for objects in the model.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: March 8, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Tal Tabakman, Yonatan Ashkenazi, Nir Paz, Yochi Bilitski
  • Publication number: 20150367293
    Abstract: Novel low-pressure nanofiltration membrane composites for rejecting organic compounds are prepared by interfacial polymerization on a microporous hollow fiber supporting membrane. The interfacial polymerization reaction is carried out using an essentially monomeric polyamine reactant having at least two amine functional groups per molecule, and an essentially monomeric amine-reactive polyfunctional aromatic or cycloaliphatic acyl halide having at least two acyl halide groups per molecule. The composite can be fabricated by stepwise polymerization reactions with different reactant recipes at each step.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 24, 2015
    Inventors: Kaimin SHIH, Guoqing ZHANG
  • Patent number: 9208282
    Abstract: In a system and method that simulates a design including a third party IP component, a driver for the IP component is compiled and executed in a workstation implementing the simulation platform for the design. The source code for the driver is modified to allow the simulation to reroute certain functions that would cause the simulator to hang until an event occurs that would unlock the simulation. The rerouting includes storing instruction location, state information, and any other context information needed to restore a paused function. The saved information is stored in a stack that is traversed upon detection of the event.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 8, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Erik S. Panu, Sandeep Suresh Pendharkar
  • Patent number: 9183331
    Abstract: A system and method that tests an IP component of a hardware design generates an abstract model of the IP component based on knowledge of the design and one or more protocols implemented with the IP component. A generic driver and associated interfaces are additionally generated or selected to test the IP component within the hardware design.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Erik S. Panu, Levent Caglar
  • Patent number: 9111560
    Abstract: An apparatus comprises a controller configured to detect a seek failure of a read/write head. The controller is additionally configured to perform a seek recovery operation in accordance with a recovery sequence in response to the seek failure; the recovery sequence comprising a plurality of recovery procedures. Further, the controller is configured to determine if the seek recovery operation is successful and determine which of the recovery procedures provided the success. And, the controller is configured to dynamically calculate the success rate of each recovery procedure, modify the recovery sequence based on the success of the seek recovery operation and based on the success rate of recovery procedures providing the success.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: August 18, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: GuoQing Zhang, Mingzhong Ding, KianKeong Ooi