Abstract: A method of matching people using a matching server includes: extracting a member profile information of a member; receiving selection data of an event; receiving selection data of a desired location; determining whether the event will occur at the desired location in the future; receiving second selection data of the event; receiving a photo of the member; receiving adjustment data; receiving filter data containing a condition of the member that matches with one or more conditions of one or more other members; outputting display data that identifies the one or more other members; receiving selection data associated with choosing the one or more other members by the member; determining whether the one or more other members has chosen the member for matching; determining one or more matches between the member and the one or more other members; and outputting notification data.

Abstract: Provided are a system for recommending related data based on similarity, and a method thereof, the system including: a data collection device; an event extraction device; a data cleansing device; an event vector generation device; an artificial intelligence learning device; and a similar data recommendation device. The present disclosure is directed to providing a system for recommending related data based on similarity and a method thereof, wherein unstructured open data on a webpage is collected to automatically generate an event label for determining a similarity relation, and an artificial intelligence (AI)-based model is trained to group and recommend semantically similar related data, thereby effectively helping users including data scientists who want to see meaningful results through open data.

Abstract: Disclosed are a novel Lactobacillus fermentum) E4 strain isolated from Kimchi which is a traditional Korean fermented food and a mass production method for the strain. The Lactobacillus fermentum E4 strain is verified to be a safe and useful probiotic strain through acid tolerance, bile acid tolerance, gelatin liquefaction, and urease tests. In addition, high DPPH free radical scavenging (%) associated with antioxidant activity was observed, and reduction in cytokines Iinterleukin-1? (IL-1?), Iinterleukin-8 (IL-8), Iinterleukin-6 (IL-6), and Toll-like receptor (TLR4), which are associated with an inflammatory response, was observed.

Abstract: There is provided a cosmetic vessel. The cosmetic vessel includes an airless pump configured to discharge cosmetics accommodated therein by using a piston that rises in a cylinder, a discharge plate provided at one side of the airless pump and having at least one discharge hole, and a guide unit provided between the airless pump and the discharge plate. A lower end of the guide unit is combined with the piston and rises or falls in a state of being integrated with the piston.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.

Abstract: Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

Abstract: A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A cosmetic vessel may include a vessel body including an inner case configured to accommodate cosmetics and having an inlet, and an outer case configured to accommodate the inner case therein and having an opening in a top thereof, a cap part coupled to the open top of the outer case, a discharge means coupled to the inlet and configured to discharge the cosmetics to an outside through a suction pipe extending to a bottom surface of the inner case, and a discharge part moving downwards to operate the discharge means and configured to transmit the cosmetics discharged from the discharge means to the outside.

Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

Abstract: A cosmetic vessel may include a vessel body including an inner case configured to accommodate cosmetics and having an inlet, and an outer case configured to accommodate the inner case therein and having an opening in a top thereof, a cap part coupled to the open top of the outer case, a discharge means coupled to the inlet and configured to discharge the cosmetics to an outside through a suction pipe extending to a bottom surface of the inner case, and a discharge part moving downwards to operate the discharge means and configured to transmit the cosmetics discharged from the discharge means to the outside.

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

Abstract: An electronic device includes a touch sensor; a touch sensor integrated circuit (IC) to detect a touch sensed by the touch sensor, a display panel, a host processor, and a display driving integrated circuit (IC) to drive the display panel such that an image received from a host processor is displayed on the display panel.

Abstract: Disclosed is a computer-readable medium including a program code that, when executed by processing circuitry, causes the processing circuitry to generate a feature map from an input image, to extract a region of interest from the feature map, and to generate a predicted mask based on the region of interest. The processing circuitry may use a predicted mask and a real mask to learn a convolutional neural network system. The real mask includes first pixels corresponding to the real boundary and second pixels corresponding to a fake boundary adjacent to the real boundary.

Abstract: A Computer-Aided Diagnosis (CAD) apparatus and a CAD method are provided. The CAD apparatus includes an automatic diagnoser configured to perform automatic diagnosis using an image that is received from a probe, and generate diagnosis information including results of the automatic diagnosis. The CAD apparatus further includes an information determiner configured to determine diagnosis information to be displayed among the generated diagnosis information, based on a manual diagnosis of a user, and a display configured to display the received image and the determined diagnosis information.

Abstract: A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.