Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

Abstract: A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.

Abstract: An apparatus and method for adaptive computer-aided diagnosis (CAD) are provided. The adaptive CAD apparatus includes an image analysis algorithm selector configured to select an image analysis algorithm based on a speed of a probe or a resolution of a current image frame obtained by the probe; and an image analyzer configured to detect and classify a region of interest (ROI) in the current image frame using the selected image analysis algorithm.

Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.

Abstract: A computer-aided diagnosis (CAD) apparatus and method. The CAD apparatus includes an area divider configured to divide a current image frame into a first area and a second area based on location of a region of interest (ROI) detected in a previous image frame. The CAD apparatus further includes a functional processor configured to perform different functions of the CAD apparatus for the first area and the second area.

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically c

Abstract: A system to generate a diagnosis model includes: a preprocessor configured to preprocess time-series data observed from a patient having a disease; a time-series analyzer configured to produce a data feature by applying an analysis model for a time-series variability analysis to the preprocessed time-series data; and a model generator configured to extract the produced data feature and to generate the diagnosis model based on the extracted produced data feature.

Abstract: Disclosed are an apparatus and method for controlling transmission power of a terminal in a wireless environment. The apparatus for controlling transmission power of a terminal includes an optimal transmission power calculation unit configured to calculate an optimal transmission power value for a terminal of a type, the terminal being accessible to one or more wireless networks; a transmission power setting unit configured to, when an access of the terminal to at least one of the one or more wireless networks is sensed, provide the terminal with optimal transmission power values corresponding to the terminal and the network accessed by the terminal.

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically c

Abstract: A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.

Abstract: A method and an apparatus are provided to visualize high-dimensional data. The method includes primarily visualizing the high-dimensional data at a dimension lower than the high-dimensional data to obtain a primarily-visualized image. The method also includes secondarily visualizing the high-dimensional data in an area of the primarily-visualized image at a dimension higher than the primarily-visualized image to obtain a secondarily-visualized image.

Abstract: A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically c

Abstract: A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.

Abstract: An apparatus for providing reliability for Computer Aided Diagnosis (CAD), including: a raw data collector configured to collect raw data containing an image acquired by a probe; an image reliability determiner configured to determine a reliability level of the image using the collected raw data; and a reliability provider configured to provide a user with the determined reliability of the image.

Abstract: A method of managing data of a file system using a database management system is provided. According to the method, the metadata of the file system is managed using a database management system (DBMS), but writing data to or reading data from a disk is directly performed by the file system according to the method directly performed not through other file systems or DBMSs. In this way, stable transactions are guaranteed for a user, and the user can design a disk allocation algorithm optimized with respect to a multimedia environment.