Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.

Abstract: A Computer-Aided Diagnosis (CAD) apparatus and a CAD method are provided. The CAD apparatus includes an automatic diagnoser configured to perform automatic diagnosis using an image that is received from a probe, and generate diagnosis information including results of the automatic diagnosis. The CAD apparatus further includes an information determiner configured to determine diagnosis information to be displayed among the generated diagnosis information, based on a manual diagnosis of a user, and a display configured to display the received image and the determined diagnosis information.

Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

Abstract: Technology related to an apparatus and method for supporting a diagnosis of a lesion is provided. The apparatus includes a standard image determiner to determine, as a standard image, an image where a region of interest (ROI) is detected among a plurality of images received from an image collecting device, a candidate image extractor to extract one or more candidate images with respect to the determined standard image, a comparison image selector to select one or more comparison images for supporting a diagnosis of the ROI from the one or more candidate images, and an interface to provide a user with an output result of the standard image and the one or more selected comparison images.

Abstract: A method of designing a layout of an integrated circuit (IC), which is implemented by a computer system or a processor, includes receiving input layout data, and performing a design rule check with regard to a plurality of patterns. The method includes, merging, from among a first pattern and a second pattern against the design rule, the first pattern with a third pattern connected to a same net as the first pattern, and generating output layout data.

Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

Abstract: A Computer-Aided Diagnosis (CAD) apparatus and a CAD method are provided. The CAD apparatus includes an automatic diagnoser configured to perform automatic diagnosis using an image that is received from a probe, and generate diagnosis information including results of the automatic diagnosis. The CAD apparatus further includes an information determiner configured to determine diagnosis information to be displayed among the generated diagnosis information, based on a manual diagnosis of a user, and a display configured to display the received image and the determined diagnosis information.

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically c

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

Abstract: There is provided a cosmetic vessel. The cosmetic vessel includes an airless pump configured to discharge cosmetics accommodated therein by using a piston that rises in a cylinder, a discharge plate provided at one side of the airless pump and having at least one discharge hole, and a guide unit provided between the airless pump and the discharge plate. A lower end of the guide unit is combined with the piston and rises or falls in a state of being integrated with the piston.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: An electronic device is provided. The electronic device includes a first display and a second display, a display module configured to display a first display screen on the first display and a second display screen on the second display, a sensing module configured to detect an event corresponding to a rotation of the electronic device, and a processor configured to respectively determine whether to rotate each of a plurality of objects included in the first display screen based on the event.

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

Abstract: A method for operating an electronic device is provided. The method includes checking context information for controlling a display divided into a first display and a second display, and controlling at least one of the first display and the second display based on the context information.

Abstract: A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.

Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop os configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.