Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

Abstract: There is provided a cosmetic vessel. The cosmetic vessel includes an airless pump configured to discharge cosmetics accommodated therein by using a piston that rises in a cylinder, a discharge plate provided at one side of the airless pump and having at least one discharge hole, and a guide unit provided between the airless pump and the discharge plate. A lower end of the guide unit is combined with the piston and rises or falls in a state of being integrated with the piston.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

Abstract: A method of visualizing anatomical elements in a medical includes receiving a medical image; detecting a plurality of anatomical elements from the medical image; verifying a location of each of the plurality of anatomical elements based on anatomical context information including location relationships between the plurality of anatomical elements; adjusting the location relationships between the plurality of anatomical elements; and combining the verified and adjusted information of the plurality of anatomical elements with the medical image.

Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.

Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

Abstract: A method of visualizing anatomical elements in a medical includes receiving a medical image; detecting a plurality of anatomical elements from the medical image; verifying a location of each of the plurality of anatomical elements based on anatomical context information including location relationships between the plurality of anatomical elements; adjusting the location relationships between the plurality of anatomical elements; and combining the verified and adjusted information of the plurality of anatomical elements with the medical image.

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

Abstract: A display operating electronic device is provided. The display operating electronic device includes a display configured to include a first output area and a second output area, a sensor module configured to detect whether the display rotates, and a processor configured to output an execution screen in the first output area and output at least one item in the second output area, and configured to replace the at least one item with at least one new item in the second output area if a pre-defined amount of rotation is detected.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.