Patents by Inventor Ha Young Kim
Ha Young Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210143181Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.Type: ApplicationFiled: January 21, 2021Publication date: May 13, 2021Inventors: JAE-WOO SEO, KI-MAN PARK, HA-YOUNG KIM, JUNGHWAN SHIN, KEUNHO LEE, SUNGWE CHO
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Publication number: 20210126014Abstract: Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.Type: ApplicationFiled: August 10, 2020Publication date: April 29, 2021Inventors: JINTAE KIM, HA-YOUNG KIM, SINWOO KIM, MOO-GYU BAE, JAEHA LEE
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Publication number: 20210118013Abstract: A method of displaying a profile view in an instant messaging service includes providing at least one set item applicable to the profile view for the personal account, applying a set item selected by the user from the set item to the profile view, providing an edit view for editing at least one profile item included in the set item applied to the profile view, and displaying a profile view edited through the edit view.Type: ApplicationFiled: October 19, 2020Publication date: April 22, 2021Inventors: Hyo Jin HAM, Ha Young KIM, So Ra LEE, Jeong Min YUN, Seong Hoon KIM, Do Yeon KIM, Ji Hwi PARK, Se Hyeong KIM, Seung Hyup HAN, Hye Mi LEE
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Publication number: 20210109623Abstract: An electronic device includes a touch sensor; a touch sensor integrated circuit (IC) to detect a touch sensed by the touch sensor, a display panel, a host processor, and a display driving integrated circuit (IC) to drive the display panel such that an image received from a host processor is displayed on the display panel.Type: ApplicationFiled: March 27, 2018Publication date: April 15, 2021Inventors: Jong Kon BAE, Han Yu Ool KIM, Matheus Farias MIRANDA, Yun Pyo HONG, Ha Young KIM, Ji Eun YANG
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Publication number: 20210075406Abstract: A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.Type: ApplicationFiled: December 24, 2019Publication date: March 11, 2021Inventors: JINTAE KIM, BYOUNGGON KANG, CHANGBEOM KIM, HA-YOUNG KIM, YONGEUN CHO
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Patent number: 10930675Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.Type: GrantFiled: October 31, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Woo Seo, Ki-Man Park, Ha-Young Kim, Junghwan Shin, Keunho Lee, Sungwe Cho
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Publication number: 20200395354Abstract: Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.Type: ApplicationFiled: March 23, 2020Publication date: December 17, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jaeha LEE, Ha-Young KIM, Bonghyun LEE, Soyoung LEE, Yongeun CHO
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Patent number: 10840244Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.Type: GrantFiled: April 1, 2019Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shigenobu Maeda, Sung Chul Park, Chul Hong Park, Yoshinao Harada, Sung Min Kang, Ji Wook Kwon, Ha-Young Kim, Yuichi Hirano
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Publication number: 20200294905Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum KIM, Ha-young KIM, Tae-joong SONG, Jong-hoon JUNG, Gi-young YANG, Jin-young LIM
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Publication number: 20200235126Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.Type: ApplicationFiled: April 8, 2020Publication date: July 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young KIM, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
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Patent number: 10720909Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.Type: GrantFiled: July 26, 2019Date of Patent: July 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-Young Kim, Dalhee Lee, Hyoung-Suk Oh, Keunho Lee, Taejoong Song, Sungwe Cho
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Publication number: 20200212069Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.Type: ApplicationFiled: March 12, 2020Publication date: July 2, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taejoong SONG, Ha-Young KIM, Jung-Ho DO, Sanghoon BAEK, Jinyoung LIM, Kwangok JEONG
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Patent number: 10691859Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.Type: GrantFiled: February 28, 2018Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Woo Seo, Ha-Young Kim, Hyun-Jeong Roh
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Patent number: 10672702Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.Type: GrantFiled: June 6, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
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Publication number: 20200161334Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.Type: ApplicationFiled: October 31, 2019Publication date: May 21, 2020Inventors: JAE-WOO SEO, KI-MAN PARK, HA-YOUNG KIM, JUNGHWAN SHIN, KEUNHO LEE, SUNGWE CHO
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Publication number: 20200152627Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.Type: ApplicationFiled: January 17, 2020Publication date: May 14, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon BAEK, Sun-Young PARK, Sang-Kyu OH, Ha-young KIM, Jung-Ho DO, Moo-Gyu BAE, Seung-Young LEE
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Patent number: 10651201Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.Type: GrantFiled: March 6, 2018Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
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Publication number: 20200117937Abstract: Disclosed is a computer-readable medium including a program code that, when executed by processing circuitry, causes the processing circuitry to generate a feature map from an input image, to extract a region of interest from the feature map, and to generate a predicted mask based on the region of interest. The processing circuitry may use a predicted mask and a real mask to learn a convolutional neural network system. The real mask includes first pixels corresponding to the real boundary and second pixels corresponding to a fake boundary adjacent to the real boundary.Type: ApplicationFiled: September 19, 2019Publication date: April 16, 2020Applicants: Samsung Electronics Co., Ltd., AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Hyunku LEE, Hyunsurk RYU, Ha Young KIM, BaRom KANG
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Publication number: 20200054113Abstract: There is provided a cosmetic vessel. The cosmetic vessel includes an airless pump configured to discharge cosmetics accommodated therein by using a piston that rises in a cylinder, a discharge plate provided at one side of the airless pump and having at least one discharge hole, and a guide unit provided between the airless pump and the discharge plate. A lower end of the guide unit is combined with the piston and rises or falls in a state of being integrated with the piston.Type: ApplicationFiled: October 23, 2019Publication date: February 20, 2020Applicant: LG HOUSEHOLD & HEALTH CARE LTD.Inventors: Se Woong OH, Ha Young KIM, Sung Hwan KIM, Sang Wook PARK, Gu Yong LEE, Ji Mi BAEK, Ok Hee JUNG
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Patent number: 10541237Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.Type: GrantFiled: July 17, 2018Date of Patent: January 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hoon Baek, Sun-Young Park, Sang-Kyu Oh, Ha-Young Kim, Jung-Ho Do, Moo-Gyu Bae, Seung-Young Lee