Patents by Inventor Hai-Dang Trinh

Hai-Dang Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190115530
    Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a lower electrode over a conductive interconnect, and an upper electrode over the lower electrode. A data storage structure is disposed between the lower electrode and the upper electrode. The data storage structure includes a plurality of metal oxide layers having one or more metals from a first group of metals. A concentration of the one or more metals from the first group of metals changes as a distance from the lower electrode increases.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Publication number: 20190109162
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 11, 2019
    Inventors: CHIH-YU LAI, MIN-YING TSAI, YEUR-LUEN TU, HAI-DANG TRINH, CHENG-YUAN TSAI
  • Publication number: 20190096753
    Abstract: The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC comprises a via dielectric layer, an adhesion layer, and a first electrode. The adhesion layer overlies the via dielectric layer, and the first electrode overlies and directly contacts the adhesion layer. The adhesion layer has a first surface energy at an interface at which the first electrode contacts the adhesion layer, and the first electrode has a second surface energy at the interface. Further, the first surface energy is greater than the second surface energy to promote adhesion. The present disclosure also relates to a method for forming the IC.
    Type: Application
    Filed: August 24, 2018
    Publication date: March 28, 2019
    Inventors: Hsing-Lien Lin, Chii-Ming Wu, Hai-Dang Trinh, Fa-Shen Jiang
  • Patent number: 10176866
    Abstract: An RRAM device is disclosed. The RRAM device includes a lower electrode structure over a conductive lower interconnect layer, an upper electrode structure over the lower electrode structure, and a switching layer between the lower electrode and the upper electrode structure. The switching layer has switching layer outer sidewalls. The RRAM device also includes a recap layer having a vertical portion that extends vertically from corners of the switching layer along the upper electrode sidewalls. The recap layer has a horizontal portion that extends horizontally from the corners to the switching layer outer sidewalls.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Hsing-Lien Lin, Hsia-Wei Chen
  • Publication number: 20180375022
    Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Patent number: 10164182
    Abstract: The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu
  • Patent number: 10164003
    Abstract: A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 10163949
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Lai, Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 10115896
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hai-Dang Trinh, Yao-Wen Chang, Cheng-Yuan Tsai, Chin-Wei Liang, Yen-Chang Chu
  • Publication number: 20180301626
    Abstract: A semiconductor device includes a first bottom electrode, a second bottom electrode, a switching layer and a top electrode. The first bottom electrode has two edges opposite to each other, and an upper surface. The second bottom electrode is between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode. The switching layer is over the first bottom electrode and the second bottom electrode. The top electrode is over the switching layer.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 18, 2018
    Inventors: HAI-DANG TRINH, YAO-WEN CHANG, CHENG-YUAN TSAI, CHIN-WEI LIANG, YEN-CHANG CHU
  • Patent number: 9978938
    Abstract: A metal-insulator-metal (MIM) capacitor structure of an RRAM device includes a first electrode and a second electrode with an insulating layer interposing the first and second electrodes. The conductive filament providing for a switching function of the RRAM device may be formed within the insulating layer. Further, a nitrogen-rich metal layer interposes the second electrode and the insulating layer. The nitrogen-rich metal layer includes a greater nitrogen concentration than that of the adjacent second electrode.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Patent number: 9954166
    Abstract: A memory cell with a composite top electrode is provided. A bottom electrode is disposed over a substrate. A switching dielectric having a variable resistance is disposed over the bottom electrode. A capping layer is disposed over the switching dielectric. A composite top electrode is disposed over and abutting the capping layer. The composite top electrode comprises a tantalum nitride (TaN) layer and a titanium nitride (TiN) film disposed directly on the tantalum nitride layer. By having the disclosed composite top electrode, an interfacial oxidized layer is eliminated or less formed when exposing the composite top electrode for top electrode via formation, thereby improving RC properties between the top electrode and the top electrode via. A method for manufacturing the memory cell is also provided.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Yao-Wen Chang
  • Publication number: 20170271383
    Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: CHIH-YU LAI, MIN-YING TSAI, YEUR-LUEN TU, HAI-DANG TRINH, CHENG-YUAN TSAI
  • Patent number: 9728597
    Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Lien Lin, Chia-Shiung Tsai, Cheng-Yuan Tsai, Huey-Chi Chu, Hai-Dang Trinh, Wen-Chuan Chiang, Wei-Min Tseng
  • Publication number: 20170207299
    Abstract: A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
    Type: Application
    Filed: April 25, 2016
    Publication date: July 20, 2017
    Inventors: HSING-LIEN LIN, HAI-DANG TRINH, CHENG-YUAN TSAI
  • Publication number: 20170141300
    Abstract: A metal-insulator-metal (MIM) capacitor structure of an RRAM device includes a first electrode and a second electrode with an insulating layer interposing the first and second electrodes. The conductive filament providing for a switching function of the RRAM device may be formed within the insulating layer. Further, a nitrogen-rich metal layer interposes the second electrode and the insulating layer. The nitrogen-rich metal layer includes a greater nitrogen concentration than that of the adjacent second electrode.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Patent number: 9647207
    Abstract: A resistive random access memory (RRAM) cell with a high ? layer based on a group-V oxide and hafnium oxide is provided. The RRAM cell includes a bottom electrode layer, a group-V oxide layer arranged over the bottom electrode layer, and a hafnium oxide based layer arranged over and abutting the group-V oxide layer. The RRAM cell further includes a capping layer arranged over and abutting the hafnium oxide based layer, and a top electrode layer arranged over the capping layer. A method for manufacturing the RRAM cell is also provided.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Chia-Shiung Tsai, Chin-Wei Liang, Cheng-Yuan Tsai, Hsing-Lien Lin, Chin-Chieh Yang, Wen-Ting Chu
  • Patent number: 9627613
    Abstract: A resistive random access memory (RRAM) cell with a composite capping layer is provided. A tantalum oxide based layer is arranged over a bottom electrode layer. The composite capping layer is arranged over and abutting the tantalum oxide based layer. The composite capping layer includes a first metal layer and a second metal layer overlying the first metal layer. The first metal layer is more reactive with the tantalum oxide based layer than the second metal layer. A top electrode layer is arranged over the composite capping layer. A method for manufacturing the RRAM cell is also provided.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Publication number: 20160276586
    Abstract: A resistive random access memory (RRAM) cell with a composite capping layer is provided. A tantalum oxide based layer is arranged over a bottom electrode layer. The composite capping layer is arranged over and abutting the tantalum oxide based layer. The composite capping layer includes a first metal layer and a second metal layer overlying the first metal layer. The first metal layer is more reactive with the tantalum oxide based layer than the second metal layer. A top electrode layer is arranged over the composite capping layer. A method for manufacturing the RRAM cell is also provided.
    Type: Application
    Filed: March 20, 2015
    Publication date: September 22, 2016
    Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin
  • Publication number: 20160218283
    Abstract: A resistive random access memory (RRAM) cell with a high ? layer based on a group-V oxide and hafnium oxide is provided. The RRAM cell includes a bottom electrode layer, a group-V oxide layer arranged over the bottom electrode layer, and a hafnium oxide based layer arranged over and abutting the group-V oxide layer. The RRAM cell further includes a capping layer arranged over and abutting the hafnium oxide based layer, and a top electrode layer arranged over the capping layer. A method for manufacturing the RRAM cell is also provided.
    Type: Application
    Filed: January 26, 2015
    Publication date: July 28, 2016
    Inventors: Hai-Dang Trinh, Chia-Shiung Tsai, Chin-Wei Liang, Cheng-Yuan Tsai, Hsing-Lien Lin, Chin-Chieh Yang, Wen-Ting Chu