Abstract: A semiconductor structure includes a first conductive layer and a second conductive layer, and a memory device between the first conductive layer and the second conductive layer. The memory device includes a top electrode, a bottom electrode adjacent to the first conductive layer, and a phase change material between the top electrode and the bottom electrode. The bottom electrode includes a first portion and a second portion between the first portion and the first conductive layer.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell. The memory cell includes a bottom electrode overlying a substrate. A data storage structure overlies the bottom electrode. A top electrode overlies the data storage structure. Sidewalls of the top electrode and sidewall of the bottom electrode are aligned. Further, a getter layer abuts the bottom electrode.

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The structure also includes a resistance variable layer over the lower electrode and an ion diffusion barrier layer over the resistance variable layer. The structure further includes a capping layer over the ion diffusion barrier layer, and the capping layer is made of a metal material. In addition, the structure includes an upper electrode over the capping layer. The structure includes a protective element extending along a sidewall of the ion diffusion barrier layer and in direct contact with an interface between the resistance variable layer and the ion diffusion barrier layer.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) device. In some embodiments, the method may be performed by forming a first electrode structure over a substrate. A doped data storage element is formed over the first electrode structure. The doped data storage element is formed by forming a first data storage layer over the first electrode structure and forming a second data storage layer over the first data storage layer. The first data storage layer is formed to have a first doping concentration of a dopant and the second data storage layer is formed to have a second doping concentration of the dopant that is less than the first doping concentration. A second electrode structure is formed over the doped data storage element.

Abstract: Various embodiments of the present disclosure are directed towards a metal-insulator-metal (MIM) capacitor including a diffusion barrier layer. A bottom electrode overlies a substrate. A capacitor dielectric layer overlies the bottom electrode. A top electrode overlies the capacitor dielectric layer. The top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnect layers and a diffusion barrier layer is arranged over the bottom electrode. A data storage layer is separated from the bottom electrode by the diffusion barrier layer. A top electrode is over the data storage layer.

Abstract: In some embodiments, the present disclosure relates to a process tool which includes a housing that defines a vacuum chamber. A wafer chuck is in the housing, and a carrier wafer is on the wafer chuck. A structure that is used for deposition processes is arranged at a top of the housing. A camera is integrated on the wafer chuck such that the camera faces a top of the housing. The camera is configured to wirelessly capture images of the structure used for deposition processes within the housing. Outside of the housing is a wireless receiver. The wireless receiver is configured to receive the images from the camera while the vacuum chamber is sealed.

Abstract: The present disclosure relates to a memory device. The memory device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate increases.

Abstract: A method for forming a semiconductor structure includes following operations. A first substrate including a first side, a second side opposite to the first side, and a metallic pad disposed over the first side is received. A dielectric structure including a first trench directly above the metallic pad is formed. A second trench is formed in the dielectric structure and a portion of the first substrate. A sacrificial layer is formed to fill the first trench and the second trench. A third trench is formed directly above the metallic pad. A barrier ring and a bonding structure are formed in the third trench. A bonding layer is disposed to bond the first substrate to a second substrate. A portion of the second side of the first substrate is removed to expose the sacrificial layer. The sacrificial layer is removed by an etchant.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer over the lower electrode, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. Oxygen ions are bonded more tightly in the second dielectric layer than those in the first dielectric layer, and oxygen ions are bonded more tightly in the second dielectric layer than those in the third dielectric layer.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a lower electrode over the semiconductor substrate. The structure also includes a resistance variable layer over the lower electrode and an ion diffusion barrier layer over the resistance variable layer. The structure further includes a capping layer over the ion diffusion barrier layer, and the capping layer is made of a metal material. In addition, the structure includes an upper electrode over the capping layer. The structure includes a protective element extending along a sidewall of the ion diffusion barrier layer and in direct contact with an interface between the resistance variable layer and the ion diffusion barrier layer.

Abstract: A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.

Abstract: The present disclosure relates to an integrated circuit (IC) comprising an adhesion layer to enhance adhesion of an electrode. In some embodiments, the IC comprises a via dielectric layer, an adhesion layer, and a first electrode. The adhesion layer overlies the via dielectric layer, and the first electrode overlies and directly contacts the adhesion layer. The adhesion layer has a first surface energy at an interface at which the first electrode contacts the adhesion layer, and the first electrode has a second surface energy at the interface. Further, the first surface energy is greater than the second surface energy to promote adhesion. The present disclosure also relates to a method for forming the IC.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.

Abstract: A structure and formation method of a semiconductor device structure is provided. The method includes forming a lower electrode layer over a semiconductor substrate and forming a data storage layer over the lower electrode layer. The method also includes forming an ion diffusion barrier layer over the data storage layer and forming a capping layer over the ion diffusion barrier layer. The ion diffusion barrier layer is a metal material doped with nitrogen, carbon, or a combination thereof. The capping layer is made of a metal material. The method further includes forming an upper electrode layer over the capping layer.