Patents by Inventor Hans Hsu

Hans Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250252677
    Abstract: The embodiments of the disclosure provide a method for improving a pass-through view and a host. The method includes: obtaining current per-frame information and historical per-frame information of the host; determining historical tracking information and texture information of a target object based on the historical per-frame information of the host; predicting current tracking information of the target object based on the historical tracking information of the target object and the current per-frame information of the host; rendering an object image corresponding to the target object based on the current tracking information and the texture information of the target object; and generating the pass-through view based on the rendered object image, the current per-frame information of the host, and the current tracking information of the target object, and displaying the pass-through view.
    Type: Application
    Filed: October 16, 2024
    Publication date: August 7, 2025
    Applicant: HTC Corporation
    Inventors: Jo-Han Hsu, Tun-Hao Chao
  • Publication number: 20250252678
    Abstract: The embodiments of the disclosure provide a method for improving a mixed reality service and a host. The method includes the following. A reference image for rendering a pass-through view is obtained from a color camera of the host. Coordinate transformation information is determined based on camera information of the host. The coordinate transformation information is used to convert a rendering position from a preset rendering position to a reference rendering position. A reference reprojection parameter is determined based on a preset reprojection parameter, the camera information of the host, and the coordinate transformation information. A virtual object corresponding to a target object to be rendered is rendered based on object information of the target object to be rendered and the coordinate transformation information. The virtual object is combined with the reference image into the pass-through view.
    Type: Application
    Filed: October 16, 2024
    Publication date: August 7, 2025
    Applicant: HTC Corporation
    Inventors: Jo-Han Hsu, Ci Syuan Yang
  • Patent number: 12354371
    Abstract: An object detection system of a vehicle includes a camera and a LIDAR sensor. The camera and the LIDAR sensor sense an environment to generate an image and a point cloud that depict the environment. The image and point cloud are preprocessed to facilitate comparison between the image and the point cloud. Similarity between the image and the point cloud in depicting the environment is determined to detect abnormal sensor data. Abnormal sensor data is further detected based on directional pattern strengths of edges of the image and expanded points of the point cloud. Detected abnormal sensor data in the image and point cloud are filtered to generate a secure image and a secure point cloud, which are provided to a perception engine to detect objects or other features in the environment.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: July 8, 2025
    Assignee: VicOne Corporation
    Inventors: Yi-Li Cheng, Jui Chang Hsu, Shih-Han Hsu
  • Patent number: 12334195
    Abstract: A computer implemented method of modifying molecular structures constrained by a budget is provided. The computer implemented method includes receiving from a user a subset of molecules, where each molecule is represented as a generation path, and receiving from the user an allotted budget for modifying a selection of molecules from the subset of molecules. The computer implemented method further includes testing a first molecule, and reducing the allotted budget based on the resources expended to test the first molecule. The computer implemented method further includes testing a second molecule, and reducing the allotted budget based on the resources expended to test the second molecule. The computer implemented method further includes determining a remaining amount of the allotted budget, and testing additional molecules from the subset of molecules until the allotted budget is exhausted. The computer implemented method further includes presenting the tested molecules to the user.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: June 17, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Akihiro Kishimoto, Toshiyuki Hama, Hsiang Han Hsu, Djallel Bouneffouf
  • Publication number: 20250192104
    Abstract: A semiconductor structure includes a first and second integrated circuit (IC) components stacked upon and electrically coupled to each other. The first IC component includes a first bonding structure including a first bonding dielectric layer and a first bonding feature disposed in the first bonding dielectric layer, and a first alignment pattern disposed in the first bonding dielectric layer. The second IC component includes a second bonding structure including a second bonding dielectric layer bonded to the first bonding dielectric layer and a second bonding feature disposed in the second bonding dielectric layer and bonded to the first bonding feature, and a second alignment pattern disposed in the second bonding dielectric layer and aligned with the first alignment pattern in a staggered manner. The second alignment pattern is disposed within a boundary of the first IC component in a top-down view.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hung Hsu, Chen Hua Huang, Tsai-Hao Hung, Cheng-Hsien Hsieh, Li-Han Hsu
  • Patent number: 12322726
    Abstract: A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Der-Chyang Yeh, Wei-Chih Lai
  • Patent number: 12320468
    Abstract: A communication apparatus and a bracket device thereof are provided. The bracket device includes a base, a rotary shaft, a connecting member, and an elastic member. The base includes a bottom portion, a connecting portion, and a base engaging portion. The rotary shaft is rotatably disposed in the connecting portion and includes a base wall and a connecting section. The connecting member connects to the rotary shaft. The elastic member includes a body and an elastic member engaging portion. The body connects to the base wall of the rotary shaft, and the elastic member engaging portion is positioned at the body. In an engagement state, the elastic member engaging portion is engaged to the base engaging portion.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: June 3, 2025
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Lan-Chun Yang, Chun-Hung Huang, Li-Han Hsu, Yi-Chieh Lin
  • Patent number: 12316361
    Abstract: The present invention discloses a signal receiving apparatus having phase compensation mechanism. A first and a second receiving path of a receiving circuit perform frequency down-conversion and analog-to-digital conversion on an input signal to generate a first and a second receiving signals. The first and the second receiving paths uses a RF training signal generated by a RF training signal generation circuit as the input signal when a phase compensation is performed, and use a data signal from an antenna circuit as the input signal when a beamforming signal receiving is performed. A phase difference calculation circuit of the receiving circuit performs cross-correlation operation on the first and the second receiving signals to generate a compensation signal according to a phase difference between the first and the second receiving paths.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: May 27, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hao-Han Hsu, Chuan-Hu Lin, Chung-Yao Chang
  • Patent number: 12271581
    Abstract: An electronic device is provided. The electronic device includes a display screen and a computing hardware which is operable to execute a software product, wherein executing the software product results in generating and rendering a graphical user interface on the display screen. When rendered, the graphical user interface presents four or more user-selectable graphical objects. Selecting and moving a first graphical object towards a second graphical object is configured to result in exchanging spatial positions of the first and second graphical objects. The exchange of the spatial positions is configured to trigger starting a timer and enabling, during a time set by the timer, selecting and moving at least a third graphical object towards a fourth graphical object. The moving the third graphical object towards the fourth graphical object is configured to result in exchanging spatial positions of the third and fourth graphical objects.
    Type: Grant
    Filed: May 6, 2024
    Date of Patent: April 8, 2025
    Assignee: Supercell Oy
    Inventors: Mikko Kodisoja, Antti Mattila, Riku Rikala, Chih-Han Hsu, Drussila Hollanda, Patrick Corander
  • Publication number: 20250105090
    Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Inventors: Chien-Chia Chiu, Li-Han Hsu
  • Publication number: 20250105174
    Abstract: A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. A seal ring within the semiconductor device is extended to include a first bond metal within a bonding layer and bonded to a second bond metal over the semiconductor substrate. Such a seal ring provided a more complete protection from cracking and delamination.
    Type: Application
    Filed: January 18, 2024
    Publication date: March 27, 2025
    Inventors: Chen Hua Huang, Cheng-Hsien Hsieh, Li-Han Hsu
  • Publication number: 20250096092
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: November 28, 2024
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Publication number: 20250087550
    Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
  • Publication number: 20250079314
    Abstract: An interconnect structure includes a conductive feature embedded in a dielectric feature. The conductive feature has a first horizontal portion and a first vertical portion. The first horizontal portion extends in a horizontal direction to terminate at two edge surfaces. The first horizontal portion includes graphene layers stacked on each other, and an intercalation material interposed among the graphene layers. The intercalation material includes a first atom dopant including one of a group 1 metal, a group 2 metal, a group 3 metal, a lanthanide series metal, an actinide series metal, and combinations thereof. The first vertical portion extends in a vertical direction and is in contact with one of the two edge surfaces of the first horizontal portion. The first vertical portion is made of a first electrically conductive metal material.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hans HSU, Shu-Wei LI, Yu-Chen CHAN, Shin-Yi YANG, Ming-Han LEE, Blanka MAGYARI-KOPE
  • Publication number: 20250065395
    Abstract: A mold moving device for a forged product forming machine includes a base unit, a transmission mechanism, a guiding member, a mold seat, and a plurality of pressing molds. The guiding member is driven by the transmission mechanism to rotate, and has an outer peripheral surface formed with a plurality of guiding grooves extending in a serpentine manner. The mold seat includes a rotary shaft, a rotating member, and a carrying member on which the pressing molds are mounted. The rotating member is connected to the rotary shaft, and includes a disk body portion and a plurality of projecting rods protruding toward the guiding member. When the guiding member rotates, the guiding grooves respectively engage selected ones of the projecting rods in a manner where the selected ones of the projecting rods respectively slide along the guiding grooves, thereby driving the disk body portion to rotate.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Inventors: Hao-Hsu LIN, Cheng-Han HSU
  • Publication number: 20250054810
    Abstract: A semiconductor structure includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and including a conductive interconnect; and a cap layer disposed on the interconnect structure. The cap layer includes a cap portion disposed on the conductive interconnect. The cap portion includes a plurality of two-dimensional material sheets stacked on each other and has a lower surface proximate to the conductive interconnect. The lower surface of the cap portion is formed with a plurality of dangling bonds such that the cap portion is adhered to the conductive interconnect through the dangling bonds.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wei LI, Hans HSU, Chien-Hsin HO, Yu-Chen CHAN, Blanka MAGYARI-KOPE, Shin-Yi YANG, Ming-Han LEE
  • Patent number: 12223045
    Abstract: Versions of an application program are evaluated to protect a customer from a supply chain attack. The versions of the application program are executed in to identify behaviors exhibited by the versions of the application program, each of the behaviors including activities that perform computer operations. A behavior change is detected by identifying a behavior that is not common to the versions of the application program.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: February 11, 2025
    Assignee: VicOne Corporation
    Inventors: Shih-Han Hsu, Wei-Jen Chang, Yao-Tang Chang, Yi-Li Cheng
  • Patent number: 12205866
    Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chia Chiu, Li-Han Hsu
  • Patent number: 12191224
    Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.
    Type: Grant
    Filed: November 6, 2022
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
  • Patent number: 12191239
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng