Patents by Inventor Hans Hsu

Hans Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230351165
    Abstract: A method is provided and includes operations as below: receiving multiple spike signals in an input layer of a spiking neural network during multiple time steps; counting a corresponding number of spikes in the spike signals for each of the time steps; weighting, in response to the corresponding number of spikes in one of plurality of time steps being greater than a predetermined count value, the spike signals with multiple synaptic weight values to generate multiple synaptic signals; generating a membrane potential by accumulating a number N of the synaptic signals according to a weight distribution of the synaptic weight values; and generating an output spike signal according to the membrane potential.
    Type: Application
    Filed: May 2, 2022
    Publication date: November 2, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Kea Tiong TANG, Chen-Han HSU
  • Patent number: 11804454
    Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 31, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Hao-Han Hsu, Dong-Ho Han, Steven C. Wachtman, Ryan K. Kuhlmann
  • Patent number: 11775155
    Abstract: An electronic device includes a display, a timer and computing hardware configured to execute a software product. Execution of the software product results in generating and rendering a graphical user interface on the display with four or more user-selectable graphical objects. Selection of a first user-selectable graphical object at a first spatial position on the graphical user interface and a movement of the selected first user-selectable graphical object along a path towards a second user-selectable graphical object at a second spatial position is detected and a position of the first user-selectable graphical object is exchanged with the position of the second user-selectable graphical object. If, during a predetermined time period, a selection of a third user-selectable graphical object and a movement of the third user-selectable graphical object towards a fourth user-selectable graphical object is detected, the positions of the third and fourth objects is exchanged.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: October 3, 2023
    Assignee: Supercell Oy
    Inventors: Mikko Kodisoja, Antti Mattila, Riku Rikala, Chih-Han Hsu, Drussila Hollanda, Patrick Corander
  • Patent number: 11769669
    Abstract: The semiconductor device includes a semiconductor fin, and a gate stack over the semiconductor fin. The gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes dopants, and a gate electrode layer over the work function material layer. The gate dielectric layer is free of the dopants.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Min Han Hsu, Jung-Chih Tsao
  • Patent number: 11756870
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Publication number: 20230283309
    Abstract: The present invention discloses a signal receiving apparatus having phase compensation mechanism. A first and a second receiving path of a receiving circuit perform frequency down-conversion and analog-to-digital conversion on an input signal to generate a first and a second receiving signals. The first and the second receiving paths uses a RF training signal generated by a RF training signal generation circuit as the input signal when a phase compensation is performed, and use a data signal from an antenna circuit as the input signal when a beamforming signal receiving is performed. A phase difference calculation circuit of the receiving circuit performs cross-correlation operation on the first and the second receiving signals to generate a compensation signal according to a phase difference between the first and the second receiving paths.
    Type: Application
    Filed: December 6, 2022
    Publication date: September 7, 2023
    Inventors: HAO-HAN HSU, CHUAN-HU LIN, CHUNG-YAO CHANG
  • Publication number: 20230282614
    Abstract: A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Der-Chyang Yeh, Wei-Chih Lai
  • Publication number: 20230280891
    Abstract: An electronic device includes a display, a timer and computing hardware configured to execute a software product. Execution of the software product results in generating and rendering a graphical user interface on the display with four or more user-selectable graphical objects. Selection of a first user-selectable graphical object at a first spatial position on the graphical user interface and a movement of the selected first user-selectable graphical object along a path towards a second user-selectable graphical object at a second spatial position is detected and a position of the first user-selectable graphical object is exchanged with the position of the second user-selectable graphical object. If, during a predetermined time period, a selection of a third user-selectable graphical object and a movement of the third user-selectable graphical object towards a fourth user-selectable graphical object is detected, the positions of the third and fourth objects is exchanged.
    Type: Application
    Filed: February 23, 2023
    Publication date: September 7, 2023
    Applicant: Supercell Oy
    Inventors: Mikko Kodisoja, Antti Mattila, Riku Rikala, Chih-Han Hsu, Drussila Hollanda, Patrick Corander
  • Patent number: 11709417
    Abstract: An illumination system and a projection device having good uniformity are provided. The illumination system includes at least one light source, a depolarizing element, and a light homogenizing element. The at least one light source is configured to provide multiple beams. The depolarizing element is disposed on a transmission path of the beams. The depolarizing element includes a first optical element, which is wedge-shaped and has a first optical axis. A direction of any one of the beams incident onto the first optical element is parallel to the first optical axis. The beams respectively become multiple linearly polarized beams with different polarization directions after passing through the first optical element. The light homogenizing element is configured to allow the linearly polarized beams to pass through to form an illumination beam. The depolarizing element is located between the at least one light source and the light homogenizing element.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: July 25, 2023
    Assignee: Coretronic Corporation
    Inventors: Yu-Sheng Chen, Jo-Han Hsu, Kuan-Ta Huang, Chi-Tang Hsieh
  • Patent number: 11705934
    Abstract: A wireless communication chip includes an analog front-end circuit and a baseband circuit. The analog front-end circuit includes a first transceiver circuit and a second transceiver circuit, wherein the first transceiver circuit is arranged to transmit or receive signals through a first antenna, and the second transceiver circuit is arranged to transmit or receive signals through a second antenna. The baseband circuit is arranged to control the first transceiver circuit to use a first band or a second band for communication, and/or to control the second transceiver circuit to use the first band or the second band for communication. The baseband circuit controls the first transceiver circuit and the second transceiver circuit so that the analog front-end circuit alternately performs 2T2R in the first band and 2T2R in the second band.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: July 18, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hao-Han Hsu, Chung-Yao Chang
  • Patent number: 11698309
    Abstract: The disclosure relates to a linear actuator including a base, a linear motor, a load cell and a rotary motor. The linear motor is disposed on the base and includes a fixed coil module and a movable magnetic backplane. The fixed coil module is fixed on the base, and the movable magnetic backplane is configured to slide relative to the fixed coil module along a first direction. The rotary motor is rotated around a central axis in parallel with the first direction. The load cell has two opposite sides parallel to the first direction, respectively. The movable magnetic backplane of the linear motor and the rotary motor are connected to the two opposite sides of the load cell, respectively. The load cell is subjected to a force applied thereto by the rotary motor and parallel to the first direction, and configured to convert the force into an electrical signal.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 11, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Han Hsu, Zi-Xuan Huang, Yu-Xian Huang, Yi-Min Liang, You-Chyau Tsai, Tsung-En Chan, Hong-Chih Chen
  • Patent number: 11693301
    Abstract: An illumination system, including a light source module, a phosphor wheel, a light recycling element, and a light uniformizing element, is provided. The light source module emits an excitation light beam. The phosphor wheel includes a phosphor region. At a second timing, the other part of the excitation light beam transmitted to the phosphor region forms an unconverted light beam and is transmitted to the light recycling element, and is reflected by the light recycling element to form a recycled light beam. A part of the recycled light beam is converted into a second converted light beam. A first converted light beam and the second converted light beam are transmitted to the light uniformizing element through a same path, so that the illumination system outputs second light in the illumination light beam. A projection apparatus is also provided.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: July 4, 2023
    Assignee: Coretronic Corporation
    Inventors: Yu-Shan Chen, Wan-Ting Hsieh, Ming-Tsung Weng, Chi-Tang Hsieh, Haw-Woei Pan, Jo-Han Hsu, Kuan-Ta Huang
  • Publication number: 20230197208
    Abstract: A computer implemented method of modifying molecular structures constrained by a budget is provided. The computer implemented method includes receiving from a user a subset of molecules, where each molecule is represented as a generation path, and receiving from the user an allotted budget for modifying a selection of molecules from the subset of molecules. The computer implemented method further includes testing a first molecule, and reducing the allotted budget based on the resources expended to test the first molecule. The computer implemented method further includes testing a second molecule, and reducing the allotted budget based on the resources expended to test the second molecule. The computer implemented method further includes determining a remaining amount of the allotted budget, and testing additional molecules from the subset of molecules until the allotted budget is exhausted. The computer implemented method further includes presenting the tested molecules to the user.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: AKIHIRO KISHIMOTO, TOSHIYUKI HAMA, Hsiang Han Hsu, Djallel BOUNEFFOUF
  • Publication number: 20230154863
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 18, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 11652063
    Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu, Tsung-Shu Lin
  • Publication number: 20230140825
    Abstract: A beam splitter/combiner includes a first light-transmitting substrate, a first light transmission element, and a second light transmission element. The first light-transmitting substrate has a first optical surface facing incident light and a second optical surface opposite to the first optical surface. The first light transmission element is disposed on the first optical surface. The second light transmission element is disposed on the second optical surface. A first color beam incident on the first light-transmitting substrate is reflected by the first light transmission element and leaves the first light-transmitting substrate. A second color beam incident on the first light-transmitting substrate passes through the first light transmission element, is reflected by the second light transmission element, then passes through the first light transmission element, and leaves the first light-transmitting substrate.
    Type: Application
    Filed: October 13, 2022
    Publication date: May 4, 2023
    Applicant: Coretronic Corporation
    Inventors: Jui Chang, Kuan-Ta Huang, Jo-Han Hsu, Chi-Tang Hsieh
  • Patent number: 11638360
    Abstract: An orientation-adjustment mechanism is provided, which is adapted to be affixed to a mounting surface. The orientation-adjustment mechanism includes a base, a rod, a joint unit, and a mounted member. The base is adapted to be affixed to the mounting surface. The rod includes a first section and a second section. The first section of the rod pivots on the base. The joint unit is disposed on the second section of the rod. The joint unit includes a plurality of joint-positioning portions. The joint-positioning portions include a first joint-positioning portion and a second joint-positioning portion. The mounted member is connected to the joint unit and is adapted to be rotated relative to the joint unit. The mounted member includes a member housing. The member housing includes at least one member-positioning portion.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: April 25, 2023
    Assignee: WISTRON NEWEB CORP.
    Inventors: Lan-Chun Yang, Chun-Hung Huang, Li-Han Hsu, Yi-Chieh Lin
  • Patent number: 11614681
    Abstract: An illumination system includes a first light source, a wavelength conversion device, a first light-splitting element, a light-filtering device, and a light-homogenizing element. The first light source provides a first light beam. The wavelength conversion device includes a single wavelength conversion material configured to convert the first light beam into a conversion light beam. The first light-splitting element is disposed on transmission paths of the first light beam and the conversion light beam. The light-filtering device is disposed on the transmission paths of the first light beam and the conversion light beam. The light-homogenizing element is disposed on the transmission paths of the first light beam and the conversion light beam. When the first light beam is transmitted to the light-homogenizing element, the first light beam is not incident on the wavelength conversion device. A projection apparatus including the illumination system is also provided.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 28, 2023
    Assignee: Coretronic Corporation
    Inventors: Haw-Woei Pan, Kuan-Ta Huang, Yu-Hua Hsieh, Jo-Han Hsu
  • Patent number: 11612057
    Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
  • Publication number: 20230074049
    Abstract: Differential signal skew compensation techniques for radio frequency interference (RFI) mitigation with no reflection penalty and associated apparatus and methods. A differential pair of signal traces are formed on or in a PCB having at least two changes in direction, with a first signal trace having a first routing path defining a first length and a second signal trace adjacent to the first signal trace including one or more tuning structures that are configured such that the length of the second signal trace matches the first length. Segments of the first signal trace adjacent to the one or more tuning structures of the second signal trace are widened relative to other segments of the first signal trace. The tuning structures may comprise sawtooth structures, accordion structures and other serpentine or meander structures. The solution mitigates RFI without a reflection penalty.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 9, 2023
    Inventors: Yingern HO, Hao-Han HSU, Boon Ping KOH