Patents by Inventor Hans Hsu

Hans Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088054
    Abstract: A carrier structure is provided with a plurality of package substrates connected via connecting sections, and a functional element and a groove are formed on the connecting section, such that the groove is located between the package substrate and the functional element. Therefore, when a cladding layer covering a chip is formed on the package substrate, the groove can accommodate a glue material overflowing from the cladding layer to prevent the glue material from contaminating the functional element.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 14, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shu-Ting LAI, Chiu-Lien LI, Che-Min SU, Chun-Huan HUNG, Mu-Hung HSIEH, Cheng-Han YAO, Fajanilan Darcyjo Directo, Cheng-Liang HSU
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20240078170
    Abstract: A setting method of in-memory computing simulator includes: performing a plurality of test combinations by an in-memory computing device and recording a plurality of first estimation indices corresponding to the plurality of test combinations respectively, wherein each of the plurality of test combinations includes one of a plurality of neural network models and one of a plurality of datasets, executing a simulator according to the plurality of test combinations by a processing device and recording a plurality of second estimation indices corresponding to the plurality of test combinations respectively, wherein the simulator has a plurality of adjustable settings; calculating a correlation sum according to the plurality of first estimation indices and the plurality of second estimation indices by the processing device, and performing an optimal algorithm to search an optimal parameter in the setting space constructed by the plurality of settings so that the correlation sum is maximal.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 7, 2024
    Inventors: Ke-Han Li, Chih-Fan Hsu, Yu-Sheng Lin, Wei-Chao CHEN
  • Publication number: 20240079758
    Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Wen-Hgin Chuang, Lin-Hsu Chiang, Chang-Hua Wu, Han-Wei Wang, Chun-Jung Hu
  • Publication number: 20240080505
    Abstract: A method, comprising: detecting an outage of at least one functionality in a live streaming; performing an first operation toward a second user terminal; storing data of the first operation in a database of the first user terminal; and displaying an effect corresponding to the first operation during the outage. The present disclosure may store the data of operation performed by the user terminal during outage and process the operation after the outage is recovered. Therefore, the streamers and viewers may feel interested and satisfied, instead of feeling anxious, and the user experience may be enhanced.
    Type: Application
    Filed: June 23, 2023
    Publication date: March 7, 2024
    Inventors: Yung-Chi HSU, Hsing-Yu TSAI, Chia-Han CHANG, Yi-Jou LEE, Ming-Che CHENG
  • Patent number: 11921101
    Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Bonraybio Co., Ltd.
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei Chang, Chiung-Han Wang
  • Publication number: 20240069677
    Abstract: A floating image generation device is disclosed, which includes a light source, an image generation module, and a floating image generation unit. The image generation module is disposed above the light source and includes a shading unit and an image generation unit. The shading unit is capable of changing light transmissivity state. The image generation unit is disposed above the shading unit. The floating image generation unit is disposed above the image generation unit. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a first floating image when the shading unit is in a first light transmissivity state. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a second floating image when the shading unit is in a second light transmissivity state.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 29, 2024
    Inventors: CHIH-PING HSU, RAN-SHIOU YOU, YU JEN LAI, YA HAN KO
  • Publication number: 20240071947
    Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
  • Publication number: 20240069704
    Abstract: An electronic device includes a display, a timer and computing hardware configured to execute a software product. Execution of the software product results in generating and rendering a graphical user interface on the display with four or more user-selectable graphical objects. Selection of a first user-selectable graphical object at a first spatial position on the graphical user interface and a movement of the selected first user-selectable graphical object along a path towards a second user-selectable graphical object at a second spatial position is detected and a position of the first user-selectable graphical object is exchanged with the position of the second user-selectable graphical object. If, during a predetermined time period, a selection of a third user-selectable graphical object and a movement of the third user-selectable graphical object towards a fourth user-selectable graphical object is detected, the positions of the third and fourth objects is exchanged.
    Type: Application
    Filed: August 29, 2023
    Publication date: February 29, 2024
    Applicant: Supercell Oy
    Inventors: Mikko Kodisoja, Antti Mattila, Riku Rikala, Chih-Han Hsu, Drussila Hollanda, Patrick Corander
  • Publication number: 20240066635
    Abstract: A laser machining device includes a pulsed laser generator, an accommodation chamber, a bandwidth broadening unit and a pulse compression unit. The pulsed laser generator is configured to emit a pulsed laser. The accommodation chamber has a gas inlet. The bandwidth broadening unit is disposed in the accommodation chamber, and is configured to broaden a frequency bandwidth of the pulsed laser to obtain a broad bandwidth pulsed laser. The pulse compression unit is disposed in the accommodation chamber. The bandwidth broadening unit and the pulse compression unit are arranged in order along a laser propagation path, and the pulse compression unit is configured to compress a pulse duration of the broad bandwidth pulsed laser.
    Type: Application
    Filed: October 5, 2022
    Publication date: February 29, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chi LEE, Bo-Han CHEN, Chih-Hsuan LU, Ping-Han WU, Zih-Yi LI, Shang-Yu HSU
  • Publication number: 20240068957
    Abstract: In an embodiment, a system includes: a broadband light source; a wafer with a first side facing the broadband light source; a first light sensor configured to detect reflected light from the broadband light source emanating from the first side; a second light sensor configured to detect emergent light emanating from a second side of the wafer opposite the first side, wherein the emergent light originates from the broadband light source; and a detector module configured to analyze the reflected light and the emergent light to identify wafer defects.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Nai-Han CHENG, Hsing-Piao Hsu
  • Patent number: 11914204
    Abstract: An optical connector device is provided. The optical connector device includes a semiconductor package including a receptacle and a lid. The optical connector device also included an adapter attached to the lid of the semiconductor package, and a connector removably attached to the adapter. The adapter includes a convex part adapted to fit into an adapter opening of the lid, an adapter recess adapted to accommodate at least a portion of the connector, and a first retainer in the adapter recess to removably attach the connector to the adapter at a predetermined position. The connector includes an optical fiber array corresponding to the receptacle and extending in a vertical direction with respect to a plane of the semiconductor package, a second retainer used in conjunction with the first retainer, and a biasing member to bias a portion of the connector toward the semiconductor package.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: February 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Masao Tokunari, Koji Masuda, Hsiang Han Hsu
  • Patent number: 11917837
    Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Yung-Han Chiu, Shu-Ming Li, Po-Yen Hsu
  • Patent number: 11917923
    Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
  • Publication number: 20240045316
    Abstract: An illumination system providing an illumination beam includes a light source module generating first to third color beams, a light splitting and combining element, a beam expanding and collimating module, a reflecting element, and a light combining module. The first and second color beams are reflected by the light splitting and combining element after being transmitted to the light splitting and combining element. Paths of the first and second color beams leaving the light splitting and combining element are coincident. The first and second color beams from the light splitting and combining element are expanded and collimated by the beam expanding and collimating module and transmitted to the light combining module. The third color beam is reflected by the reflecting element and transmitted to the light combining module. Paths of the first to third color beams after leaving the light combining module are coincident. A projection device is provided.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 8, 2024
    Applicant: Coretronic Corporation
    Inventors: Jui Chang, Kuan-Ta Huang, Jo-Han Hsu
  • Publication number: 20240027884
    Abstract: An illumination system includes first to third reflection components, a first light splitting and combining element, and a lens. The first and second reflection components reflect a first color beam and another first color beam, respectively. The third reflection element reflects a second color beam and another second color beam. The first light splitting and combining element passes the second color beams and reflects the first color beams. The first color beams and the second color beams leaving the first light splitting and combining element respectively form first and second irradiation areas not overlapped with each other and third and fourth irradiation areas not overlapped with each other on the lens, and each of the first and second irradiation areas are overlapped with at least a portion of the third and fourth irradiation areas.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 25, 2024
    Applicant: Coretronic Corporation
    Inventors: Jui Chang, Kuan-Ta Huang, Jo-Han Hsu
  • Publication number: 20240011079
    Abstract: The present invention relates to a nucleic acid detection chip, the method and detection equipment using the same. The test sample injects into the first injection hole on the slip plate into the groove on the substrate through the first guide hole. The test sample is heated to the first temperature and then cooled down. Displacing the top plate to align the second injection hole and the hole of the substrate. Injecting the light conversion material into the hole of the substrate to generate a detection sample. Displacing the plate again to move the detection sample to the substrate's top of the detection hole. Exposing the detection sample with the first light to generate the second light by the light conversion material in the detection sample. By absorbing the second light to generate a current that is closely dependent on the concentration of light conversion material in the detection sample.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 11, 2024
    Inventors: CHAO-AN JONG, WANWIPA SIRIWATWECHAKUL, SHU-HAN HSU, YU-FENG CHENG, PAIBOON SREEARUNOTHAI, THILINA RAJEENDRE KATUGAMPALAGE
  • Patent number: 11860527
    Abstract: An illumination system including an excitation light source array, a multi-region dichroic device, a color sequence generator, and a wavelength converter is provided. The excitation light source array emits excitation light beams. The multi-region dichroic device has first dichroic regions and non-dichroic regions that are alternately arranged in stripe shapes. The first dichroic regions are respectively disposed on transmission paths of the excitation light beams. The excitation light beams from the excitation light source array are transmitted to the color sequence generator through the first dichroic regions of the multi-region dichroic device, and at least one second dichroic region of the color sequence generator respectively reflects the excitation light beams to the non-dichroic regions of the multi-region dichroic device. The excitation light beams from the color sequence generator are transmitted to the wavelength converter through the non-dichroic regions of the multi-region dichroic device.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 2, 2024
    Assignee: Coretronic Corporation
    Inventors: Haw-Woei Pan, Jo-Han Hsu, Kuan-Ta Huang, Chi-Tang Hsieh
  • Publication number: 20230402429
    Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.
    Type: Application
    Filed: January 9, 2023
    Publication date: December 14, 2023
    Inventors: Chien-Fu Tseng, Yu Chieh Yung, Cheng-Hsien Hsieh, Hung-Pin Chang, Li-Han Hsu, Wei-Cheng Wu, Der-Chyang Yeh
  • Publication number: 20230369189
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng