Patents by Inventor Hao Hsu

Hao Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • USER EQUIPMENT MOBILITY WITH SPECIFIC UPLINK BANDWIDTH PART
    Publication number: 20230269651
    Abstract: Certain aspects of the present disclosure provide techniques for wireless communication by a user equipment (UE). According to certain aspects, a UE may be configured to detect, in a first bandwidth part (BWP), a condition triggering a mobility procedure that involves a physical random access channel (PRACH) transmission in a second BWP, determining a timeline for transmitting the PRACH in the second BWP, based on a mobility procedure delay that accounts for BWP switching time for switching from the first BWP to the second BWP, and transmitting the PRACH in the second BWP in accordance with the timeline.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 24, 2023
    Inventors: Prashant SHARMA, Muhammad Nazmul ISLAM, Chun-Hao HSU, Yongle WU
  • CONTACT FEATURES OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
    Publication number: 20230260836
    Abstract: A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 17, 2023
    Inventors: Pei Shan Chang, Yi-Hsiang Chao, Chun-Hsien Huang, Peng-Hao Hsu, Kevin Lee, Shu-Lan Chang, Ya-Yi Cheng, Ching-Yi Chen, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Methods of forming integrated circuit packages
    Patent number: 11728314
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Voltage supply selection circuit
    Patent number: 11728789
    Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Cheng Hung Lee, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Semiconductor package with heat dissipation films and manufacturing method thereof
    Patent number: 11728238
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
  • Power management circuit, system-on-chip device, and method of power management
    Patent number: 11726539
    Abstract: A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Cheng Hung Lee, Hung-Jen Liao
  • SRAM with tracking circuitry for reducing active power
    Patent number: 11727972
    Abstract: A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Huang, Wei-Jer Hsieh, Yu-Hao Hsu
  • HIGH THROUGHPUT AND HIGH POSITION ACCURATE METHOD FOR PARTICLE INSPECTION OF MASK PODS
    Publication number: 20230251581
    Abstract: In a method of inspecting an outer surface of a mask pod, a stream of air is directed at a first location of a plurality of locations on the outer surface. One or more particles are removed by the directed stream of air from the first location on the outer surface. Scattered air from the first location of the outer surface is extracted and a number of particles in the extracted scattered air is determined as a sampled number of particles at the first location. The mask pod is moved and the stream of air is directed at other locations of the plurality of locations to determine the sampled number of particles in extracted scattered air at the other locations. A map of the particles on the outer surface of the mask pod is generated based on the sampled number of particles at the plurality of locations.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 10, 2023
    Inventors: Shih-Jui HUANG, ShinAn KU, Ting-Hao HSU, Hsin-Chang LEE
  • Semiconductor device and operation method thereof
    Patent number: 11722099
    Abstract: A device includes a substrate, a first electrode and a second electrode. The first electrode is disposed on the substrate, and configured to receive an input signal. The second electrode is disposed on the substrate, and configured to output an output signal based on the input signal. When the input signal is configured to oscillate within a first range between a first voltage value and a second voltage value with a first frequency, the output signal is an inverted version of the input signal, and has the first frequency. When the input signal is configured to oscillate within a second range including the first voltage value without the second voltage value with the first frequency, the output signal has a second frequency which is approximately twice of the first frequency.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: August 8, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Ting-Hao Hsu
  • IODINATED COMPOUNDS AND HYDROGELS FORMED FROM SAME
    Publication number: 20230241295
    Abstract: In some aspects, the present disclosure pertains to systems for forming hydrogels that comprise (a) a first composition that comprises a polyiodinated polyamino compound that comprises a polyamino moiety linked to a polyiodinated aromatic moiety by an amide group or ester group and (b) a second composition that comprises a reactive multi-arm polymer that comprises a plurality of hydrophilic polymer arms having reactive end groups that are reactive with amino groups of the polyiodinated polyamino compound. Other aspects of the present disclosure pertain to medical hydrogels and methods of making medical hydrogels that are based on such compositions. Further aspects of the present disclosure pertain to methods of making polyiodinated polyamino compounds.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 3, 2023
    Applicant: Boston Scientific Scimed, Inc.
    Inventors: Joseph Thomas Delaney, JR., Yen-Hao Hsu, Tatyana Dyndikova
  • SRAM POWER-UP RANDOM NUMBER GENERATOR
    Publication number: 20230245696
    Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Inventors: Jui-Che Tsai, Chen-Lin Yang, Yu-Hao Hsu, Shih-Lien Linus Lu
  • MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20230238384
    Abstract: A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 27, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Ting-Hao HSU
  • SEMICONDUCTOR PACKAGE HAVING LIQUID-COOLING LID
    Publication number: 20230238302
    Abstract: A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Sheng-Liang Kuo, Bo-Jiun Yang
  • Power control scheme for active bandwidth part transition
    Patent number: 11711772
    Abstract: Disclosed are techniques for wireless communication. In an aspect, BS transmits first and second configurations for first and second BWPs to UE. The first BWP is set as an active BWP based on the first configuration. BS transmits TCP command(s) that set an active power control adjustment state. BS transitions the active BWP from the first BWP to the second BWP based on the second configuration. The active power control adjustment state is maintained after the active BWP transition (e.g., not reset to some default state).
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: July 25, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Chun-Hao Hsu, Nachiket Nanadikar, Dinesh Kumar Devineni, Deepak Wadhwa
  • Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure
    Patent number: 11705413
    Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: July 18, 2023
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • SRS POSITIONING BWP IN RRC INACTIVE OR IDLE POSITIONING
    Publication number: 20230224934
    Abstract: Methods, apparatuses, and computer-readable storage medium for wireless communication are provided. An example method may include transmitting, to a network entity, a capability for a transmission of one or more positioning SRS outside of an initial UL BWP during an idle state or an inactive state of the UE. The example method may further include receiving, from the network entity, a configuration for the transmission of the one or more positioning SRS outside of the initial UL BWP during the idle state or the inactive state. The example method may further include transmitting, to the network entity based on the configuration, the one or more positioning SRS outside of the initial UL BWP.
    Type: Application
    Filed: May 27, 2022
    Publication date: July 13, 2023
    Inventors: Alexandros MANOLAKOS, Peter GAAL, Carlos CABRERA MERCADER, Jae Ho RYU, Yongle WU, Chun-Hao HSU
  • CONTACT FEATURES OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
    Publication number: 20230223302
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Application
    Filed: May 13, 2022
    Publication date: July 13, 2023
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • SEMICONDUCTOR PACKAGE STRUCTURE HAVING ANTENNA ARRAY
    Publication number: 20230207499
    Abstract: A semiconductor package structure is provided. The structure includes a package substrate having a first surface and a second surface opposite to the first surface and including a ground layer embedded therein. A semiconductor die is formed on the first surface of the package substrate and an antenna pattern layer is formed on the second surface of the package substrate and electrically coupled to the semiconductor die. The structure also includes a first connector and a second connector formed on the second surface of the package substrate and arranged adjacent to the antenna pattern layer. The first connector is electrically coupled to the semiconductor die and electrically isolated to the ground layer, and the second connector is electrically coupled to the ground layer. A wireless communication device including the semiconductor package structure is also provided.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 29, 2023
    Inventors: Wun-Jian LIN, Shih-Huang YEH, Chen-Hao HSU
  • VOLTAGE REGULATOR WITH POWER RAIL TRACKING
    Publication number: 20230185324
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Configurable memory storage system
    Patent number: 11675505
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin