Abstract: A multilevel converter system is provided. The system includes a converter and a converter controller interfaced with the converter. The converter controller includes a voltage loop, a current loop, and a voltage compensation loop. The voltage loop is configured to receive first and second voltages from the first and second segments of the converter and a reference voltage. The current loop is configured to receive a current output of the converter, a reference current, and a balancing reference current. The voltage compensation loop is configured to receive the first and second voltages and a sign signal. The converter controller is configured to generate first and second pulse-width modulation (PWM) signals using output signals from the current loop and the output compensation signals from the voltage compensation loop. The PWM signals are configured to control the switches of the converter and to balance the first voltage with the second voltage.

Abstract: Methods for chemical mechanical polishing (CMP), and methods for forming an interconnect structure of a semiconductor device are provided. The methods include performing CMP on a surface of a dielectric structure with a CMP slurry to remove a portion of a metal layer formed in the dielectric structure and having at least a first layer exposed through the surface. In some examples, the CMP slurry that includes an abrasive, an oxidizing agent, and a compound configured to reduce aggregation of the abrasive on the surface of the dielectric structure. In some examples, the compound has positively charged ions that interact with the abrasive to reduce aggregation of the abrasive on a dielectric material. In some examples, the CMP slurry includes potassium hydroxide. In some examples, the compound includes an ammonium salt.

Abstract: Provided are a tool and a method for processing a semiconductor wafer. A processing method includes supporting a semiconductor wafer continuously along a periphery of the semiconductor wafer with an electrically grounded conductive member; and spinning the semiconductor wafer, wherein surface charges induced during spinning are dissipated by movement of electrons from the semiconductor wafer to the electrically grounded conductive member at the periphery of the semiconductor wafer.

Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.

Abstract: A method comprising: providing a slurry to a polishing pad that is disposed on a wafer platen, the slurry comprising a plurality of electrically charged abrasive particles having a first electrical polarity; moving a first side of a wafer into contact with the slurry and the polishing pad; applying a first electrical charge having a second electrical polarity, opposite the first electrical polarity, to a first conductive rod; moving the first side of the wafer away from the polishing pad while the first electrical charge is applied to the first conductive rod; moving a first wafer brush into contact with the first side of the wafer; applying a second electrical charge having the second electrical polarity, opposite the first electrical polarity, to a second conductive rod arranged within the first wafer brush; and moving the first wafer brush away from the first side of the wafer.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: Various examples are provided related to dynamic nonlinear droop control (DNDC). In one embodiment, a method for DNDC for direct current (DC) power conversion includes receiving an indication of an output of a DC power converter, generating a control signal based upon the indication, and adjusting operation of the DC power converter in response to the generated control signal. The indication can be a scaled measurement of output current or output power of the DC power converter. The control signal is based at least in part upon the indication, the power converter voltage and DNDC parameters.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A converter includes a DC bus, a first DC-DC converter, a second DC-DC converter, and a plurality of circulating current suppression circuits. The first DC-DC converter is coupled to the DC bus and includes a first plurality of switches. The second DC-DC converter is coupled to the DC bus in parallel with the first DC-DC converter. The second DC-DC converter includes a second plurality of switches. The plurality of circulating current suppression circuits are coupled to the DC bus and are further respectively coupled to the first DC-DC converter and the second DC-DC converter. Each of the plurality of circulating current suppression circuits has a resonant frequency at or around a switching frequency for the first and second pluralities of switches. The plurality of circulating current suppression circuits is configured to suppress current at or around the switching frequency and pass at least direct current.

Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.

Abstract: A multilevel converter system is provided. The multilevel converter system includes a multilevel converter and a short-circuit protection circuit. The multilevel converter includes a first segment and a second segment electrically connected to the first segment, wherein the first and second segments are each configured to convert a first current to a second current. The first segment includes a plurality of first switches. The second segment includes a plurality of second switches. The short-circuit protection circuit is electrically connected to the multilevel converter, wherein the short-circuit protection circuit includes at least one electrical component that is electrically connected in parallel with at least one of the plurality of first switches and the plurality of second switches. The short-circuit protection circuit is configured to protect the plurality of first switches and the plurality of second switches from a short-circuit current during a short-circuit condition.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: Provided herein are methods for producing crystalline tungsten bronze oxide particles. The method may include atomizing a liquid solution comprising an alkali metal precursor and a tungsten precursor to produce droplets; mixing the droplets with one or more gaseous flows to produce a combined flow; flowing the combined flow through a heated reactor to provide crystalline tungsten bronze oxide particles having the formula MxWO3, wherein M is the alkali metal; and collecting the particles.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A converter includes a DC bus, a first DC-DC converter, a second DC-DC converter, and a plurality of circulating current suppression circuits. The first DC-DC converter is coupled to the DC bus and includes a first plurality of switches. The second DC-DC converter is coupled to the DC bus in parallel with the first DC-DC converter. The second DC-DC converter includes a second plurality of switches. The plurality of circulating current suppression circuits are coupled to the DC bus and are further respectively coupled to the first DC-DC converter and the second DC-DC converter. Each of the plurality of circulating current suppression circuits has a resonant frequency at or around a switching frequency for the first and second pluralities of switches. The plurality of circulating current suppression circuits is configured to suppress current at or around the switching frequency and pass at least direct current.

Abstract: A multilevel converter system is provided. The system includes a converter and a converter controller interfaced with the converter. The converter controller includes a voltage loop, a current loop, and a voltage compensation loop. The voltage loop is configured to receive first and second voltages from the first and second segments of the converter and a reference voltage. The current loop is configured to receive a current output of the converter, a reference current, and a balancing reference current. The voltage compensation loop is configured to receive the first and second voltages and a sign signal. The converter controller is configured to generate first and second pulse-width modulation (PWM) signals using output signals from the current loop and the output compensation signals from the voltage compensation loop. The PWM signals are configured to control the switches of the converter and to balance the first voltage with the second voltage.