Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.

Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A translation method is provided, including: encoding to-be-processed text information to obtain a source vector representation sequence, the to-be-processed text information belonging to a first language; obtaining a source context vector corresponding to a first instance according to the source vector representation sequence, the source context vector indicating to-be-processed source content in the to-be-processed text information at the first instance; determining a translation vector according to the source vector representation sequence and the source context vector; and decoding the translation vector and the source context vector, to obtain target information of the first instance, the target information belonging to a second language.

Abstract: A magnetic coupling, includes a driving rotor sleeved on the driving shaft, a driven rotor sleeved on the driven shaft, external magnets mounted on the driving rotor and internal magnets mounted on the driven rotor and located on the inner sides of the external magnets; a plurality of internal magnets are arranged and uniformly distributed along the circumferential direction of the driven rotor; the external magnets and the internal magnets are aligned one by one along a radial direction; the internal magnets and the external magnets are magnetized along the radial direction; adjacent internal magnets have opposite magnetizing directions, and adjacent external magnets have opposite magnetizing directions; magnetic poles of the internal magnets are opposite to magnetic poles of the corresponding external magnets, and the driving rotor and the driven rotor form a working magnetic circuit through a magnetic field generated by the external magnets and a magnetic field generated by the internal magnets, wherein at

Abstract: A converter includes a DC bus, a first DC-DC converter, a second DC-DC converter, and a plurality of circulating current suppression circuits. The first DC-DC converter is coupled to the DC bus and includes a first plurality of switches. The second DC-DC converter is coupled to the DC bus in parallel with the first DC-DC converter. The second DC-DC converter includes a second plurality of switches. The plurality of circulating current suppression circuits are coupled to the DC bus and are further respectively coupled to the first DC-DC converter and the second DC-DC converter. Each of the plurality of circulating current suppression circuits has a resonant frequency at or around a switching frequency for the first and second pluralities of switches. The plurality of circulating current suppression circuits is configured to suppress current at or around the switching frequency and pass at least direct current.

Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.

Abstract: A multilevel converter system is provided. The multilevel converter system includes a multilevel converter and a short-circuit protection circuit. The multilevel converter includes a first segment and a second segment electrically connected to the first segment, wherein the first and second segments are each configured to convert a first current to a second current. The first segment includes a plurality of first switches. The second segment includes a plurality of second switches. The short-circuit protection circuit is electrically connected to the multilevel converter, wherein the short-circuit protection circuit includes at least one electrical component that is electrically connected in parallel with at least one of the plurality of first switches and the plurality of second switches. The short-circuit protection circuit is configured to protect the plurality of first switches and the plurality of second switches from a short-circuit current during a short-circuit condition.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: Provided herein are methods for producing crystalline tungsten bronze oxide particles. The method may include atomizing a liquid solution comprising an alkali metal precursor and a tungsten precursor to produce droplets; mixing the droplets with one or more gaseous flows to produce a combined flow; flowing the combined flow through a heated reactor to provide crystalline tungsten bronze oxide particles having the formula MxWO3, wherein M is the alkali metal; and collecting the particles.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A converter includes a DC bus, a first DC-DC converter, a second DC-DC converter, and a plurality of circulating current suppression circuits. The first DC-DC converter is coupled to the DC bus and includes a first plurality of switches. The second DC-DC converter is coupled to the DC bus in parallel with the first DC-DC converter. The second DC-DC converter includes a second plurality of switches. The plurality of circulating current suppression circuits are coupled to the DC bus and are further respectively coupled to the first DC-DC converter and the second DC-DC converter. Each of the plurality of circulating current suppression circuits has a resonant frequency at or around a switching frequency for the first and second pluralities of switches. The plurality of circulating current suppression circuits is configured to suppress current at or around the switching frequency and pass at least direct current.

Abstract: A multilevel converter system is provided. The system includes a converter and a converter controller interfaced with the converter. The converter controller includes a voltage loop, a current loop, and a voltage compensation loop. The voltage loop is configured to receive first and second voltages from the first and second segments of the converter and a reference voltage. The current loop is configured to receive a current output of the converter, a reference current, and a balancing reference current. The voltage compensation loop is configured to receive the first and second voltages and a sign signal. The converter controller is configured to generate first and second pulse-width modulation (PWM) signals using output signals from the current loop and the output compensation signals from the voltage compensation loop. The PWM signals are configured to control the switches of the converter and to balance the first voltage with the second voltage.

Abstract: A multilevel converter system is provided. The multilevel converter system includes a multilevel converter and a short-circuit protection circuit. The multilevel converter includes a first segment and a second segment electrically connected to the first segment, wherein the first and second segments are each configured to convert a first current to a second current. The first segment includes a plurality of first switches. The second segment includes a plurality of second switches. The short-circuit protection circuit is electrically connected to the multilevel converter, wherein the short-circuit protection circuit includes at least one electrical component that is electrically connected in parallel with at least one of the plurality of first switches and the plurality of second switches. The short-circuit protection circuit is configured to protect the plurality of first switches and the plurality of second switches from a short-circuit current during a short-circuit condition.

Abstract: An earphone case includes a body, a storage member, a cover, and a reset member. The body has a chamber and a fixing base. The base is securely disposed in the chamber. The storage member is disposed in the chamber, located above the fixing base, contacted with the body, and has multiple first magnetic parts. The cover is pivotally connected to the storage member and the fixing base, and the cover has multiple second magnetic parts. The reset member is disposed above the fixing base and connected to the body and the storage member respectively. In close mode, the cover completely covers the storage member. The multiple first magnetic parts and second magnetic parts are magnetically attracted to each other. In open mode, the cover is relatively separated from the storage member and rotated at an angle, such that the cover partially overlaps with the storage member.

Abstract: A control circuit for a power converter is provided. The control circuit includes a pulse width modulator, a current feedback loop, a bus voltage feedforward path, and a logic circuit. The pulse width modulator generates a control signal for the power converter to regulate a load current. The current feedback loop controls the pulse width modulator to converge the load current to a demanded current. The bus voltage feedforward path measures a bus voltage supplied to the power converter at an input bus and, in combination with the current feedback loop, control the pulse width modulator to regulate the load current based on the bus voltage. The logic circuit collects load current measurements and determines, based at least partially thereon, a voltage variation event has occurred on the input bus, and disables the control signal for the power converter in response to determining the voltage variation event has occurred.