Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.

Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

Abstract: A light-emitting device packaging structure is provided. The light-emitting device packaging structure includes a substrate, an array of light-emitting devices, an encapsulating layer, scattering particles, and a fluorescent material layer. The array of light-emitting devices is on the substrate. The encapsulating layer covers the array of light-emitting devices. The scattering particles are dispersed in the encapsulating layer. The fluorescent material layer is on the encapsulating layer.

Abstract: A charge device coupled to an external device is provided. A connection port is configured to couple to the external device and includes a first pin and a second pin. A battery unit has a battery voltage. A conversion unit converts the battery voltage to provide power to the external device. When the battery voltage is higher than a threshold value, a detection control unit directs the first and second pins to couple to a first charge unit and the connection port outputs a first charge current to the external device. When the battery voltage is not higher than the threshold value, the detection control unit directs the first and second pins to couple to a second charge unit and the connection port outputs a second charge current to the external device. The first charge current is greater than the second charge current.

Abstract: A method for manufacturing a patterned layer includes the steps of: providing a substrate having a first surface and a second surface opposite to the first surface; providing a material source for supplying a plurality of charged particles, in which the first surface faces the material source; providing a magnetic element, in which the second surface is arranged between the magnetic element and the first surface; and depositing the charged particles on the first surface through using the magnetic element so as to form a patterned layer. A method for manufacturing an electrochromic device is disclosed as well.

Abstract: A three-dimensional display device includes a display panel and a barrier structure. The barrier structure is located at one side of the display panel. Besides, the barrier structure includes a plurality of barrier patterns and a plurality of transparent slits. The barrier patterns and the transparent slits are arranged alternately. In particular, the barrier patterns include a photoelectric conversion structure.

Abstract: A power tracking device and a power tracking method is disclosed herein. The power tracking device includes a power voltage setting circuit, a switch, a switching signal circuit, and a voltage memory circuit. The switching signal circuit is configured for sending a first control signal to the switch. When the switch receives the first control signal and electrically isolates the power source and the power voltage setting circuit, the voltage memory circuit stores an open circuit voltage of the power source and sends a setting voltage relative to the open circuit voltage, and when the switch receives the first control signal and electrically connects the power source and the power voltage setting circuit, the power voltage setting circuit sets an output voltage of the power source to correspond with the setting voltage.

Abstract: A charge device coupled to an external device is provided. A connection port is configured to couple to the external device and includes a first pin and a second pin. A battery unit has a battery voltage. A conversion unit converts the battery voltage to provide power to the external device. When the battery voltage is higher than a threshold value, a detection control unit directs the first and second pins to couple to a first charge unit and the connection port outputs a first charge current to the external device. When the battery voltage is not higher than the threshold value, the detection control unit directs the first and second pins to couple to a second charge unit and the connection port outputs a second charge current to the external device. The first charge current is greater than the second charge current.

Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.

Abstract: An RF receiver/transmitter apparatus for carrier aggregation is disclosed, to provide a routing circuitry formed by a plurality of mixer modules for achieving both the function of carrier aggregation and the mixing frequency process of signals. This architecture allows sharing an RF front-end, improving degree of integration, and reducing hardware cost and circuitry power consumption. In addition, in the process of reception and transmission, the apparatus may perform different processing and configuration for each sub-channel to increase circuit design flexibility. The receiver apparatus includes at least one antenna, a first signal processing unit, a routing mixer device, a second signal processing unit and a digital signal processor (DSP); and the routing mixer device includes a plurality of mixer module and a plurality of current/voltage adders to achieve signal routing control through opening or closing of the mixer, switching the signal transmission path or switching the signal synthesizer.

Abstract: A method for manufacturing a patterned layer includes the steps of: providing a substrate having a first surface and a second surface opposite to the first surface; providing a material source for supplying a plurality of charged particles, in which the first surface faces the material source; providing a magnetic element, in which the second surface is arranged between the magnetic element and the first surface; and depositing the charged particles on the first surface through using the magnetic element so as to form a patterned layer. A method for manufacturing an electrochromic device is disclosed as well.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.

Abstract: The embodiments described herein relate to a reconfigurable energy storage system. In one embodiment, the reconfigurable energy storage system comprises a first energy storage system, a second energy storage system and a power converter. The power converter determines a first power level, a second power level and a load coupled to the power converter and manipulates the power transfer between the energy storage systems based on the first power level, the second power level and the load. In another embodiment, the reconfigurable energy storage system also comprises a third energy storage system. In this embodiment, the power converter determines a third power level corresponding to the third energy storage system and manipulates the power transfer between the energy storage systems based also on the third power level. The third power level may correspond to a state of charge of the third energy storage element or amount of power generated by the third energy storage system.

Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

Abstract: An electronic apparatus and a display thereof are disclosed. The display includes a back plate, a photoelectric converting module, and a display module. The back plate has an inner surface and an open is formed on the back plate. The back plate has an inner edge around the open. The inner edge is concave toward the direction back to inner surface to form a supporting part. The photoelectric converting module is disposed on the supporting part without protruding out of the inner surface. The photoelectric converting module has a light-receiving surface exposed to the open. The display module is disposed on the inner surface of the back plate and the display module covers the photoelectric converting module. The display module has a display surface back to the photoelectric converting module.

Abstract: An electronic device including a display unit and a photoelectric conversion board is provided. The display unit includes a display surface and a back surface which are opposite to each other, and an edge of the photoelectric conversion board is rotatably connected to the back surface of the display unit. The photoelectric conversion board includes a substrate, a first photoelectric conversion unit, and a second photoelectric conversion unit. The substrate has a first surface and a second surface which are opposite to each other, the first photoelectric conversion unit is disposed on the first surface, the second photoelectric conversion unit is disposed on the second surface, and an absorption band of the first photoelectric conversion unit is different from an absorption band of the second photoelectric conversion unit.