Abstract: An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.

Abstract: Method and system for calibrating a plurality of voltages of a light-emitting element and a plurality of grayscale values of a respective pixel of the light-emitting element on a display panel are provided. The method may include determining a mapping correlation between the plurality of voltages of the light-emitting element and a plurality of luminance values of the light-emitting element, determining N grayscale values of the pixel, and determining N first luminance values each corresponding to the respective one of the N grayscale values. The method may also include determining N first voltages mapped to the N first luminance values using the mapping correlation and determining, of each one of the N first luminance values, (M?1) second luminance values. Each one of the (M?1) second luminance values may correspond to a different dimmed luminance value of the respective first luminance value.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.

Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: A compensating mechanism includes a base, an adjusting unit, an adjusting cap and a stop unit. The adjusting unit is disposed on the base. The adjusting cap is configured to move the adjusting unit with respect to the base so as to form a first circumferential movement range. The stop unit includes a sliding element and a limiting element, wherein the limiting element includes a movement region, and the adjusting cap is configured to move the sliding element along the movement region so as to form a second circumferential movement range. A sum of a first central angle corresponding to the first circumferential movement range and a second central angle corresponding to the second circumferential movement range is a fixed value. A sight is provided to include a main body, an objective unit, an ocular unit, an inner lens barrel and the compensating mechanism.

Abstract: A compensating mechanism includes a base, an adjusting unit, an adjusting cap and a stop unit. The adjusting unit is disposed on the base. The adjusting cap is configured to move the adjusting unit with respect to the base so as to form a first circumferential movement range. The stop unit includes a sliding element and a limiting element, wherein the limiting element includes a movement region, and the adjusting cap is configured to move the sliding element along the movement region so as to form a second circumferential movement range. A sum of a first central angle corresponding to the first circumferential movement range and a second central angle corresponding to the second circumferential movement range is a fixed value. The invention also provides a sight, wherein the sight includes a main body, an objective unit, an ocular unit, an inner lens barrel and the compensating mechanism.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: The embodiments described herein relate to a reconfigurable energy storage system. In one embodiment, the reconfigurable energy storage system comprises a first energy storage system, a second energy storage system and a power converter. The power converter determines a first power level, a second power level and a load coupled to the power converter and manipulates the power transfer between the energy storage systems based on the first power level, the second power level and the load. In another embodiment, the reconfigurable energy storage system also comprises a third energy storage system. In this embodiment, the power converter determines a third power level corresponding to the third energy storage system and manipulates the power transfer between the energy storage systems based also on the third power level. The third power level may correspond to a state of charge of the third energy storage element or amount of power generated by the third energy storage system.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A compensating mechanism includes a base, an adjusting unit, an adjusting cap and a stop unit. The adjusting unit is disposed on the base. The adjusting cap is configured to move the adjusting unit with respect to the base so as to form a first circumferential movement range. The stop unit includes a sliding element and a limiting element, wherein the limiting element includes a movement region, and the adjusting cap is configured to move the sliding element along the movement region so as to form a second circumferential movement range. A sum of a first central angle corresponding to the first circumferential movement range and a second central angle corresponding to the second circumferential movement range is a fixed value. The invention also provides a sight, wherein the sight includes a main body, an objective unit, an ocular unit, an inner lens barrel and the compensating mechanism.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

Abstract: An ultrasonic rock salt continuous cleaning method and an ultrasonic rock salt continuous cleaning device are provided. The ultrasonic rock salt continuous cleaning method comprises, in a loading and pre-examining stage, loading and pre-examining a solid substance, where first sample information of the solid substance is collected; in a pre-cleaning stage, pre-cleaning the solid substance, wherein a cleaning fluid is applied; in an ultrasonic cleaning stage, ultrasonic cleaning the solid substance; in a drying stage, drying the solid substance, where the solid substance is dried in two stages, in a first stage, the solid substance is dried using a high-pressure air, and in a second stage, the solid substance is dried using hot air; and in an unloading and examining stage, unloading and examining the rock salts, where second sample information of the solid substance is collected.

Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.