Abstract: A control circuit for a power converter is provided. The control circuit includes a pulse width modulator, a current feedback loop, a bus voltage feedforward path, and a logic circuit. The pulse width modulator generates a control signal for the power converter to regulate a load current. The current feedback loop controls the pulse width modulator to converge the load current to a demanded current. The bus voltage feedforward path measures a bus voltage supplied to the power converter at an input bus and, in combination with the current feedback loop, control the pulse width modulator to regulate the load current based on the bus voltage. The logic circuit collects load current measurements and determines, based at least partially thereon, a voltage variation event has occurred on the input bus, and disables the control signal for the power converter in response to determining the voltage variation event has occurred.

Abstract: A method and device for measuring dominant wavelength and color purity of LED lamp, and an electronic equipment.

Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

Abstract: The present application provides a testing apparatus. The testing apparatus includes a base; a first printed circuit board, disposed above the base; a stiffener, disposed adjacent to the base, located at a center of the base and passing through the first printed circuit board; a second printed circuit board, disposed at a center of the stiffener; and a probe card, one part thereof disposed adjacent to the stiffener and the other part thereof passing through the base, the first printed circuit board, the stiffener and the second printed circuit board. The base, the stiffener and the second printed circuit board are integrated and the base carries the first circuit board.

Abstract: A method and device for measuring dominant wavelength and color purity of LED lamp, and an electronic equipment.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: Method and system for calibrating a plurality of voltages of a light-emitting element and a plurality of grayscale values of a respective pixel of the light-emitting element on a display panel are provided. The method may include determining a mapping correlation between the plurality of voltages of the light-emitting element and a plurality of luminance values of the light-emitting element, determining N grayscale values of the pixel, and determining N first luminance values each corresponding to the respective one of the N grayscale values. The method may also include determining N first voltages mapped to the N first luminance values using the mapping correlation and determining, of each one of the N first luminance values, (M?1) second luminance values. Each one of the (M?1) second luminance values may correspond to a different dimmed luminance value of the respective first luminance value.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.

Abstract: An earphone case includes a body, a storage member, a cover, and a reset member. The body has a chamber and a fixing base. The base is securely disposed in the chamber. The storage member is disposed in the chamber, located above the fixing base, contacted with the body, and has multiple first magnetic parts. The cover is pivotally connected to the storage member and the fixing base, and the cover has multiple second magnetic parts. The reset member is disposed above the fixing base and connected to the body and the storage member respectively. In close mode, the cover completely covers the storage member. The multiple first magnetic parts and second magnetic parts are magnetically attracted to each other. In open mode, the cover is relatively separated from the storage member and rotated at an angle, such that the cover partially overlaps with the storage member.

Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Abstract: An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.

Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.

Abstract: A compensating mechanism includes a base, an adjusting unit, an adjusting cap and a stop unit. The adjusting unit is disposed on the base. The adjusting cap is configured to move the adjusting unit with respect to the base so as to form a first circumferential movement range. The stop unit includes a sliding element and a limiting element, wherein the limiting element includes a movement region, and the adjusting cap is configured to move the sliding element along the movement region so as to form a second circumferential movement range. A sum of a first central angle corresponding to the first circumferential movement range and a second central angle corresponding to the second circumferential movement range is a fixed value. A sight is provided to include a main body, an objective unit, an ocular unit, an inner lens barrel and the compensating mechanism.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.