Abstract: An RF receiver/transmitter apparatus for carrier aggregation is disclosed, to provide a routing circuitry formed by a plurality of mixer modules for achieving both the function of carrier aggregation and the mixing frequency process of signals. This architecture allows sharing an RF front-end, improving degree of integration, and reducing hardware cost and circuitry power consumption. In addition, in the process of reception and transmission, the apparatus may perform different processing and configuration for each sub-channel to increase circuit design flexibility. The receiver apparatus includes at least one antenna, a first signal processing unit, a routing mixer device, a second signal processing unit and a digital signal processor (DSP); and the routing mixer device includes a plurality of mixer module and a plurality of current/voltage adders to achieve signal routing control through opening or closing of the mixer, switching the signal transmission path or switching the signal synthesizer.

Abstract: An interface circuit for an image receiving apparatus is disclosed. The interface circuit includes a plurality of signal transporting units, and each of the signal transporting units has a first signal receiving terminal and a second signal receiving terminal for receiving a first input signal and a second input signal respectively. Each of the signal transporting units compares the first input signal and the second input signal to generate a compare result. Each of the signal transporting units outputs the first input signal and the second input signal and/or the compare result according to a setting mode.

Abstract: A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.

Abstract: A method of forming cell spheroids cultured in a serum-free manner on nanoscale coatings of hyaluronic acid with high molecular weight is disclosed. Corneal stromal cells are cultured on the hyaluronic acid coatings with nanotopography in the serum-free manner. Experimental results show that the cells cultured on the hyaluronic acid coatings (1.1-1.7 nm) increase cell-cell interaction, and when the cells form three-dimensional spheroids, they have higher biological synthetic capabilities and can secret more extracellular matrix, which has potential applications in corneal stromal tissue reconstruction.

Abstract: A solar power system includes a solar cell module, a main system and at least one sub system. The solar cell module includes at least one first solar cell unit and one second solar cell unit coupled in series. The first solar cell unit is configured to have an available maximum output current greater than that of the second solar cell unit. The main system is electrically coupled to the solar cell module and simultaneously supplied with electrical power by the first solar cell unit and the second solar cell unit both. The at least one sub system is electrically coupled to the solar cell module and supplied with electrical power by the first solar cell unit only. A solar cell module and a power providing method thereof are also provided.

Abstract: A power tracking device and a power tracking method is disclosed herein. The power tracking device includes a power voltage setting circuit, a switch, a switching signal circuit, and a voltage memory circuit. The switching signal circuit is configured for sending a first control signal to the switch. When the switch receives the first control signal and electrically isolates the power source and the power voltage setting circuit, the voltage memory circuit stores an open circuit voltage of the power source and sends a setting voltage relative to the open circuit voltage, and when the switch receives the first control signal and electrically connects the power source and the power voltage setting circuit, the power voltage setting circuit sets an output voltage of the power source to correspond with the setting voltage.

Abstract: A solar cell module is provided and includes a first solar cell and a second solar cell. The first solar cell includes a first metal substrate, a first photoelectric conversion layer, a first top electrode layer, a first P-N junction semiconductor, and a first bottom electrode layer. The second solar cell includes a second metal substrate, a second photoelectric conversion layer, a second top electrode layer, a second P-N junction semiconductor, and a second bottom electrode layer. The first photoelectric conversion layer and the first P-N junction semiconductor are respectively located on two opposite sides of the first metal substrate. The second photoelectric conversion layer and the second P-N junction semiconductor are respectively located on two opposite sides of the second metal substrate. The second bottom electrode layer is located on the second P-N junction semiconductor, and is electrically coupled to the first metal substrate.

Abstract: An electronic device includes a multi-field sensor, a memory, and a codec wrapper module, in which the codec wrapper module includes at least one encoder and at least one decoder. The encoder compresses raw data of an image into an image bit stream with a compression ratio through the following steps. The image is segmented into various image bands. Storage space is allocated in the memory and is segmented into various compressed band regions according to the compression ratio and a bit stream length of the raw data. A starting position of each compressed band region is recorded as a current ending position. Lines, sequentially received, are compressed into compressed bit streams respectively. The compressed bit streams are sequentially written into the corresponding compressed band regions according to field indexes of the lines, an output field order, and a group formed by the image bands corresponding to the lines.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.

Abstract: An interface circuit for an image receiving apparatus is disclosed. The interface circuit includes a plurality of signal transporting units, and each of the signal transporting units has a first signal receiving terminal and a second signal receiving terminal for receiving a first input signal and a second input signal respectively. Each of the signal transporting units compares the first input signal and the second input signal to generate a compare result. Each of the signal transporting units outputs the first input signal and the second input signal and/or the compare result according to a setting mode.

Abstract: A solar cell module includes multiple solar cells connected in series through wiring units. Each solar cell comprises an electrode unit disposed on a photoelectric conversion unit converting solar energy into electrical energy, and including multiple finger electrodes. At least one finger electrode has a first conducting section connected to a bus bar electrode, and a second conducting section disposed on one side of the first conducting section, extending away from the bus bar electrode and having a thickness greater than that of each of the first conducting section and the bus bar electrode.

Abstract: A three-dimensional display device includes a display panel and a barrier structure. The barrier structure is located at one side of the display panel. Besides, the barrier structure includes a plurality of barrier patterns and a plurality of transparent slits. The barrier patterns and the transparent slits are arranged alternately. In particular, the barrier patterns include a photoelectric conversion structure.

Abstract: A photovoltaic package includes a substrate, a photovoltaic cell, an electric device, a cover, and an encapsulating material. The photovoltaic cell is disposed on the substrate. The electric device is disposed on the substrate and is electrically connected to the photovoltaic cell. The cover covers the substrate, the photovoltaic cell, and the electric device. The cover has a first depression formed therein. The first depression receives at least a portion of the electric device. The encapsulating material is located between the substrate and the cover. The encapsulating material at least partially encapsulates the photovoltaic cell and the electric device.

Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.

Abstract: An electronic apparatus and a display thereof are disclosed. The display includes a back plate, a photoelectric converting module, and a display module. The back plate has an inner surface and an open is formed on the back plate. The back plate has an inner edge around the open. The inner edge is concave toward the direction back to inner surface to form a supporting part. The photoelectric converting module is disposed on the supporting part without protruding out of the inner surface. The photoelectric converting module has a light-receiving surface exposed to the open. The display module is disposed on the inner surface of the back plate and the display module covers the photoelectric converting module. The display module has a display surface back to the photoelectric converting module.

Abstract: An electronic device includes a multi-field sensor, a memory, and a codec wrapper module, in which the codec wrapper module includes at least one encoder and at least one decoder. The encoder compresses raw data of an image into an image bit stream with a compression ratio through the following steps. The image is segmented into various image bands. Storage space is allocated in the memory and is segmented into various compressed band regions according to the compression ratio and a bit stream length of the raw data. A starting position of each compressed band region is recorded as a current ending position. Lines, sequentially received, are compressed into compressed bit streams respectively. The compressed bit streams are sequentially written into the corresponding compressed band regions according to field indexes of the lines, an output field order, and a group formed by the image bands corresponding to the lines.

Abstract: A system for power management electrically connected to a solar cell is provided. The system for power management includes a photo-sensor, a controller electrically connected to the photo-sensor, and a power manager. The photo-sensor detects an illumination (illuminance or irradiance) of an environment where the solar cell is located. A look-up table of illumination vs. maximum output power is built in the controller, wherein a corresponding maximum output power is determined by the controller according to the illumination detected by the photo-sensor. The power manager is electrically connected to the controller and the solar cell. The power manager controls the output current of the solar cell so as to equalize an output power of solar cell and the corresponding maximum output power. A method for power management is also provided.

Abstract: A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.

Abstract: An oxide semiconductor thin film transistor structure includes a substrate, a gate electrode disposed on the substrate, a semiconductor insulating layer disposed on the substrate and the gate electrode, an oxide semiconductor layer disposed on the semiconductor insulating layer, a patterned semiconductor layer disposed on the oxide semiconductor layer, and a source electrode and a drain electrode respectively disposed on the patterned semiconductor layer. The source electrode and the drain electrode are made of a metal layer.