Abstract: The disclosure provides a to-be-tested object extraction apparatus and a nucleic acid testing integrated machine with the to-be-tested object preparation apparatus.

Abstract: Provided is a flexible display substrate, including: a peripheral region and a display region. The peripheral region surrounds the display region. The peripheral region has a plurality of corner regions, and at least one of the corner regions includes two first regions and a second region disposed between the two first regions. The first region has a hollow structure, and the second region has at least one notch disposed in an edge of the flexible display substrate.

Abstract: The present invention relates to a method for the manufacture of a compound of Formula I or a pharmaceutically acceptable salt, acid co-crystal, hydrate or other solvate thereof, said method comprising reacting a compound of the formula II with a compound of the formula III according to the following reaction scheme: wherein LG, A, n, m and p are as defined in the Summary of the Invention.

Abstract: A flexible circuit board and a display module are provided. The flexible circuit board includes: a flexible substrate having a chip binding region; a driving chip, arranged in the chip binding region of the flexible substrate; and a protective layer, arranged on a side of the driving chip away from the flexible substrate, where the protective layer includes an electrostatic discharge layer, an orthographic projection of the electrostatic discharge layer on the flexible substrate at least partially overlaps with an orthographic projection of the driving chip on the flexible substrate.

Abstract: The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

Abstract: The disclosure provides a to-be-tested object processing apparatus and a nucleic acid testing integrated machine with the to-be-tested object processing apparatus.

Abstract: Provided are compositions and methods useful for inserting a larger nucleic acid fragment to a target genome sequence. The editing system employs a pair of pegRNA which, by virtue of their targeting nearby genomic sites and having sequences complementary to each other, collectively form a template for inserting a large exogenous sequence to the target genomic locus.

Abstract: Provided is a sample analysis device, including: a housing, a reagent preparation apparatus, a sample processing apparatus, and an analysis apparatus. A first independent space, a second independent space and a third independent space are sequentially arranged in the housing at intervals. The reagent preparation apparatus is arranged in the first independent space. The sample processing apparatus is arranged in the second independent space, a first conveying channel is arranged between the reagent preparation apparatus and the sample processing apparatus, a first switching piece is arranged at the first conveying channel, and the first switching piece has a first opening state and a first closing state.

Abstract: An integrated chip including a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first photodetector and a second photodetector are in the first semiconductor substrate. A trench isolation layer at least partially surrounds the first photodetector and the second photodetector and extends between the first photodetector and the second photodetector. The trench isolation layer has a first pair of sidewalls. The first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls, to the second photodetector. The doped region is between the first pair of sidewalls. The first photodetector and a first gate partially form a first transistor. The second photodetector and a second gate partially form a second transistor. A second semiconductor substrate is over the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

Abstract: 3D object detection is a computer vision task that generally detects (e.g. classifies and localizes) objects in 3D space from the 2D images or videos that capture the objects. Current techniques used for 3D object detection rely on machine learning processes that learn to detect 3D objects from existing images annotated with high-quality 3D information including depth information generally obtained using lidar technology. However, due to lidar's limited measurable range, current machine learning solutions to 3D object detection do not support detection of 3D objects beyond the lidar range, which is needed for numerous applications, including autonomous driving applications where existing close or midrange 3D object detection does not always meet the safety-critical requirement of autonomous driving. The present disclosure provides for 3D object detection using a technique that supports long-range detection (i.e. detection beyond the lidar range).

Abstract: A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.

Abstract: A computing device for verifying data integrity is provided, comprising a memory controller configured to receive a plurality of original data blocks. Each original data block has an associated initial CRC value. The memory controller then segments and recombines the received data blocks into logic blocks, and calculates a new logic block CRC value for each logic block. The logic blocks are transmitted with their respective new logic block CRC values to a storage device, and the logic blocks are written to non-volatile memory of the storage device in a write operation. After the write operation, a combined CRC value is calculated for the logic blocks and a combined CRC value for the original data blocks, and compare the combined CRC values. The memory controller determines whether the combined CRC values match. When they match, the memory controller generates a verification response verifying the integrity of the write operation.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

Abstract: A balun structure and an electronic device. The balun structure includes: a dielectric substrate; a first grounding conductive layer, a first transmission line, a second transmission line, and a third transmission line, wherein at least one coupling structure is connected in series between a first end and a second end of the third transmission line. The coupling structure includes a first coupling part and a second coupling part, wherein in the same coupling structure, one end of the first coupling part facing the second coupling part has at least one first branch line, and one end of the second coupling part facing the first coupling part has at least one second branch line; and in the same coupling structure, the first branch line of the first coupling part is in coupling connection with the second branch line of the second coupling part.

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.