Abstract: A diode structure includes a nanosheet structure on a substrate, including a first, first-type diffusion region, a second, first-type diffusion region on the substrate, a first, second-type diffusion region, and a second, second-type diffusion region, each on the substrate. The diode structure includes a first gate on the nanosheet structure between the first and second, first-type diffusion regions. The diode structure includes a first frontside zero (M0) metal layer coupled to a frontside of the first and second, first-type diffusion regions, and a first backside M0 metal layer coupled to a backside of the first and second, first-type diffusion regions to form an anode. The diode structure includes a second frontside M0 metal layer coupled to a frontside of the first and second, second-type diffusion regions, and a second backside M0 metal layer coupled to a backside of the first and second, second-type diffusion regions to form a cathode.

Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.

Abstract: Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: A method for detecting a display panel defect, including: collecting a panel image of a to-be-detected display panel, a plurality of first pixels of the display panel corresponding to a plurality of second pixels in the panel image; converting the panel image into a binary image; dilating each bright spot region in the binary image such that adjacent bright spot regions communicate with each other to form at least one closed communication region in the binary image; determining a region of interest mask image in the binary image in accordance with the at least one closed communication region; determining a region of interest in accordance with the region of interest mask image and the panel image; and performing feature identification on the region of interest to determine a defect of the display panel.

Abstract: An apparatus includes a secondary controller coupled to a secondary circuit of a power conversion system, and a primary controller coupled to a primary circuit of the power conversion system, the primary controller being coupled to the secondary controller through an isolation interface, wherein the secondary controller is configured to detect whether a load is coupled to the power conversion system, in response to the load being disconnected from the power conversion system, communicate with the primary controller through pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time, provide a high impedance at the secondary feedback node to reduce power consumption, and in response to the load being reconnected to the power conversion system, communicate with the primary controller through pulling down the secondary feedback node in the secondary circuit for a second predetermined time.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.

Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.

Abstract: A package structure includes a package substrate, an organic interposer and an electronic unit. The package substrate includes a plurality of first pads. The organic interposer is disposed on the package substrate and includes a plurality of second pads. The second pads are directly connected to the first pads to electrically connected the organic interposer to the package substrate. At least one of each of the first pads and each of the second pads includes a pad portion and a plurality of contact portions connecting the pad portion. A first extension direction of the pad portion is different from a second extension direction of the contact portions. The electronic unit is disposed on the organic interposer, wherein the electronic unit is electrically connected to the package substrate through the organic interposer.

Abstract: Provided are a method and an apparatus for implementing batch extraction of human anatomical feature parameters. The method includes: obtaining a to-be-measured sample; generating an average model; calculating a point correspondence of a spatial location formed by the average model and each to-be-measured sample; measuring each to-be-measured sample on the average model; and outputting feature parameter data of each to-be-measured sample in batch. Calculation time is reduced by combining feature point extraction with affine transformation, and corresponding points are calculated through a non-rigid registration method to achieve batch and quick measurement.

Abstract: A controlling method for semiconductor process auxiliary apparatus, a control assembly and a manufacturing system are provided. The controlling method includes the following steps. At least one manufacturing parameter of a semiconductor manufacturing processing apparatus are obtained. An energy adjusting signal is generated according to the manufacturing parameter. An auxiliary apparatus controlling signal is generated according to the energy adjusting signal. The semiconductor process auxiliary apparatus is controlled according to the semiconductor auxiliary apparatus controlling signal.

Abstract: Provided are a method and apparatus for evaluating anatomical adaptation of an implantable orthopedic medical device. The method includes: obtaining an anatomical adaptation region of a to-be-evaluated bone with the implantable orthopedic medical device; determining a baseline of the anatomical adaptation region and a baseline of the implantable orthopedic medical device for position registration, and conducting the position registration for the anatomical adaptation region and the implantable orthopedic medical device based on the baselines; and evaluating adhesion of the to-be-evaluated bone to the implantable orthopedic medical device by calculating a distance from each point on an inner curved surface of the implantable orthopedic medical device to the anatomical adaptation region.

Abstract: A semiconductor device includes first channel members, a first gate structure wrapping around each of the first channel members, a first epitaxial feature abutting the first channel members, second channel members, a second gate structure wrapping around each of the second channel members, a second epitaxial feature abutting the second channel members, and an isolation feature has a first portion laterally stacked between the first and second gate structures and a second portion laterally stacked between the first and second epitaxial features. A width of the first portion of the isolation feature is larger than a width of the second portion of the isolation feature.

Abstract: One or more controllers, after activation of a vehicle, may charge and discharge a traction battery according to power limits that are based on polarization voltages describing internal states of the traction battery and that are a function of polarization voltages present at a last deactivation of the vehicle and decay values having time constants that are based on a state of charge of the traction battery and a temperature associated with the traction battery.

Abstract: Disclosed are displacement sensors constructed from optical fibers having a long elongation with low-cost ToF sensors that advantageously do not suffer the infirmities of the art. The ToF sensor and the optical fiber ends that launch and receive light are packaged such that no ambient light affects measurements, and the structure is protected from contamination which eliminates optical degradation. With multi-point measurement capabilities and the low-cost features of ToF sensors, many displacement sensors can be arranged in a mesh to map out displacements over a large area and over all directions for civil and/or geotechnical structures. Wireless or other communications mechanisms may be employed in conjunction with our novel sensors to send real time measurement data to a central office for real time monitoring and analysis.

Abstract: Provided is a sensing and adaptation method for exercise. The method is applied to a sensing and adaptation device for exercise and includes the following steps: generating an exercise game and a first resistance setting to an exercise equipment according to a first exercise target data; receiving an exercise interactive data of a user operating the exercise game from the exercise equipment; generating a reaction-time data according to a stage data of the exercise game and the exercise interactive data and generating an operation trajectory data according to the first resistance setting, the stage data and the exercise interactive data; calculating a deviation degree of the operation trajectory data; calculating a second exercise target data according to the deviation degree; generating a second resistance setting and updating the exercise game according to the second exercise target, and transmitting the second resistance setting to the exercise equipment.

Abstract: An external rotation 3D lidar device and a simultaneous localization and mapping (SLAM) method comprises a 3D hybrid solid-state lidar device that is driven to rotate by an external motor. The device significantly improves the horizontal field of view of the lidar and can be mounted on a ground robot to comprehensively improve its 360-degree environment sensing capabilities. Error-state Kalman filtering and pose graph optimization are combined and the overall framework is divided into two parts: front-end odometry and back-end loop-closure optimization. Therefore, high-frequency odometry that meets the requirements of the robot can be output in real time and cumulative errors can be eliminated through the back-end loop-closure optimization.

Abstract: The present invention discloses a pyrrolidine derivative or its optically active isomer, or a pharmaceutically acceptable salt thereof, which is useful as an NAMPT inhibitor, and useful as a potential agent for the chemotherapy of a variety of diseases associated with abnormal NAD+ expression. The pyrrolidine derivative has pyrrolidine as a parent structure, to which pyridinylurea (or substituted pyridinylurea) is attached by an intermediate aliphatic chain, and a side arylformyl (or heterocyclylformyl) group is attached. This structure is an optimized structure of the NAMPT inhibitor FK866, in which the acrylamido group is replaced by a urea structure, to increases the water solubility of the compound. Moreover, the difficulty in synthesis is reduced accordingly, which is conducive to the subsequent industrial production.

Abstract: The present invention provides a refrigerator door with a replaceable door panel, comprising: a foam door body, and a front panel detachably connected to the foam door body; a first limiting member and a second limiting member are disposed on a front side of the foam door body; a frame is sandwiched between the front panel and the foam door body, the frame is attached to a rear side of the front panel, a hook is disposed on the frame, and the hook has an insertion plate portion; wherein when the front panel is assembled on the front side of the foam door body, the first limiting member, in cooperation with the insertion plate portion, limits a displacement of the front panel in a first direction; the second limiting member, in cooperation of the frame, limits a displacement of the front panel in a second direction.