Patents by Inventor Hao Wang

Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11997821
    Abstract: A tray assembly is detachably disposed on a casing and includes a tray body, at least one gear set, a handle, and at least one side cover. The tray body is adapted to be accommodated in the casing. The least one gear set is disposed at a side of the tray body. The at least one gear set has a first engagement portion configured to be engaged with the casing. The handle is rotatably connected to the tray body via the at least one gear set. The at least one side cover is fixed to the tray body and covers the at least one gear set.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 28, 2024
    Assignee: WISTRON CORP.
    Inventors: Jun-Hao Wang, Yisheng Chen, Siyun Tan, Li Ke
  • Patent number: 11997328
    Abstract: Disclosed are a hypertext transfer protocol (HTTP) request transmission method and device. The HTTP request transmission method and device resolve a problem that data finally obtained through splicing is invalid because dividing an original HTTP request into a plurality of HTTP requests to pull data from different content distribution network (CDN) servers may cause inconsistency of the pulled data. When an electronic device needs to download data from a plurality of CDN servers, an overlapping range may be designed for byte ranges allocated to the different CDN servers. This means that the electronic device downloads data in the overlapping range from all the different CDN servers. Therefore, this part of data is used to check consistency of the data pulled from the different CDN servers. When determining that the data pulled from the different CDN servers is consistent, the electronic device may splice the data to obtain finally required data.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: May 28, 2024
    Assignees: Huawei Technologies Co., Ltd., PEKING UNIVERSITY
    Inventors: Hao Wang, Zheng Hu, Chenren Xu, Xingmin Guo, Xiaojin Li, Zhiyong Yan
  • Patent number: 11997854
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11996334
    Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11997736
    Abstract: A connection establishment method includes a terminal device obtaining historical data of a multipath transmission control protocol (MPTCP) connection established between the terminal device and an application server. The historical data includes a data transmission delay of a transmission control protocol (TCP) connection corresponding to a Wi-Fi network and a data transmission delay of a TCP connection corresponding to a cellular network. The terminal device determines, based on the historical data, that the data transmission delay of the TCP connection corresponding to the cellular network is less than or equal to the data transmission delay of the TCP connection corresponding to the Wi-Fi network, and establishes a first TCP connection to the application server through an interface of the cellular network; and after the first TCP connection is successfully established, the terminal device establishes a second TCP connection to the application server through an interface of the Wi-Fi network.
    Type: Grant
    Filed: November 30, 2019
    Date of Patent: May 28, 2024
    Assignees: Huawei Technologies Co., Ltd., Peking University
    Inventors: Hao Wang, Songping Yao, Chenren Xu, Fanzhao Wang, Xingmin Guo, Xiangli Li, Zhiyu Chen
  • Patent number: 11996481
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Patent number: 11993863
    Abstract: A metal product includes a metal substrate, at least one first hole, at least one second hole, and at least one third hole. The first hole is formed in a surface of the metal substrate. The second hole is formed in at least one of a portion of the surface of the metal substrate without the first hole and an inner surface defining the first hole. The third hole is formed in at least one of a portion of the surface of the metal substrate without the first hole and without the second hole, a portion of the inner surface defining the first hole without the second hole, and an inner surface defining the second hole. The first, second, and third holes enhance a bonding strength between the metal product and a material product. The disclosure also provides a metal composite and a method for manufacturing the metal product.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 28, 2024
    Assignee: Fulian Yuzhan Precision Technology Co., Ltd
    Inventors: Yu-Mei Hu, Shi-Chu Xue, Li-Ming Shen, Zheng-Quan Wang, Dong-Xu Zhang, Zhong-Hua Mai, An-Li Qin, Qing-Rui Wang, Ching-Hao Yang, Kar-Wai Hon, Hao Zhou
  • Patent number: 11996461
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11996332
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Ting Pan, Chih-Hao Wang, Kuo-Cheng Chiang, Yi-Bo Liao, Yi-Ruei Jhan
  • Patent number: 11992706
    Abstract: Provided is a simulation phantom including a simulated target volume and a simulated normal tissue encasing the simulated target volume, wherein the simulated target volume and a portion of the simulated normal tissue abutting the simulated target volume have a first characteristic to enable the simulation phantom to be imaged on a first imaging device, and the simulated target volume and the portion of the simulated normal tissue abutting the simulated target volume further have a second characteristic to enable the simulation phantom to be imaged on a second imaging device different from the first imaging device.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 28, 2024
    Assignee: OUR UNITED CORPORATION
    Inventors: Zhongya Wang, Hao Yan, Jiuliang Li
  • Patent number: 11992407
    Abstract: Disclosed is a multi-layered composite bionic self-retaining prosthesis for a femoral shaft, including a scaffold, an upper bone plate, and a lower bone plate. An upper outer side of the scaffold is fixed to a low inner side of the upper bone plate, and a lower outer side of the scaffold is fixed to an upper inner side of the lower bone plate. The scaffold includes an upper trabeculae layer, a middle cortical bone layer and a lower trabeculae layer. The middle cortical bone layer is a multi-layered composite structure which includes an outer frame layer, a middle filling layer and an inner frame layer. The upper and lower bone plates each include an inner trabeculae layer and an outer reinforcement layer.
    Type: Grant
    Filed: August 23, 2023
    Date of Patent: May 28, 2024
    Assignee: JILIN UNIVERSITY
    Inventors: Zhihui Qian, Yue Lu, Jincheng Wang, Lei Ren, Hao Chen, Kunyang Wang, Kaize Wang, Guangsheng Song, Youhao Diao, Luquan Ren
  • Patent number: 11996483
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11994011
    Abstract: The present invention discloses a permanent packer and an extended gas lift method using the permanent packer, the method comprising: S1. imbedding the extended gas lift embedded pipe when setting the permanent packer, wherein the extended gas lift embedded pipe has an upper end being closed and a lower end being open, is provided therein with a one-way valve through which the fluid can pass from top to bottom; S2. lowering a breaking device from the production casing when in the extended gas lift, to break the upper end of the extended gas lift embedded pipe such that the upper and lower ends of the extended gas lift embedded pipe are communicated; and S3. injecting gas into the production casing, lifting the accumulated liquid in the bottom hole to the ground surface, to complete the extended gas lift.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 28, 2024
    Assignees: PetroChina Company Limited, Sichuan Shengnuo Oil. and Gas Engineering Technology Service Co. Ltd
    Inventors: Weilin Wang, Huiyun Ma, Changqing Ye, Hao Tan, Hanbing Tang, Daogang Cai, Xueqiang Wang, Yukui Hong, Fengjing Sun, Wei Zhou, Ting Zhang, Zonghao Dong, Yan Huang, Yun Miao
  • Patent number: 11994762
    Abstract: Provided is a liquid crystal handwriting board. The liquid crystal handwriting board includes: a liquid crystal panel, and a drive assembly electrically connected to the liquid crystal panel; wherein the liquid crystal panel includes: a first substrate and a second substrate that are opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate; and the drive assembly is configured to apply, based on position information of a region to be erased, a pixel voltage to a pixel electrode in the region to be erased in the case that the liquid crystal handwriting board is in an erasing mode, such that a voltage difference is developed between the pixel electrode in the region to be erased and the common electrode.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: May 28, 2024
    Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yang Ge, Yu Zhao, Xiaojuan Wu, Jiaxing Wang, Xian Wang, Huairui Yue, Jianwei Ma, Hailong Wang, Dawei Feng, Hao Yan
  • Patent number: 11995405
    Abstract: The present disclosure provides a multi-lingual model training method, apparatus, electronic device and readable storage medium and relates to the technical field of deep learning and natural language processing. A technical solution of the present disclosure when training the multi-lingual model is: obtaining training corpuses comprising a plurality of bilingual corpuses and a plurality of monolingual corpuses; training a multi-lingual model with a first training task by using the plurality of bilingual corpuses; training the multi-lingual model with a second training task by using the plurality of monolingual corpuses; and completing the training of the multi-lingual model in a case of determining that loss functions of the first training task and second training task converge.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 28, 2024
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Xuan Ouyang, Shuohuan Wang, Chao Pang, Yu Sun, Hao Tian, Hua Wu, Haifeng Wang
  • Patent number: 11996298
    Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11996410
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chien Cheng, Chih-Hao Wang, Guan-Lin Chen, Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng
  • Publication number: 20240167626
    Abstract: Disclosed are a processing apparatus, a corrugated plate, and a storage container. The processing apparatus includes a pair of slide plates, a pair of press plates, a shaping block, and a driving mechanism. The driving mechanism includes a slide plate driving portion linked to a shaping block driving portion, allowing the slide plate driving portion drives the pair of slide plates to approach each other at a first predetermined speed, the shaping block driving portion moves the shaping block downward at a second predetermined speed, and the first and second predetermined speed are specifically correlated with respect to a predetermined forming profile of an intersection portion. The processing apparatus of the present disclosure causes running speeds of various portions that move in different directions to extrude a blank plate to be specifically associated, so that the formation process is particularly applicable to a corrugated plate having the predetermined corrugated shape.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Fengqi LI, Jian ZHANG, Ying WEI, Xiangao FENG, Wei HE, Kang WANG, Qingfeng YIN, Ming LI, Hao WU
  • Publication number: 20240169167
    Abstract: The present disclosure provides a method for anti-tampering apparatus servicing data implemented by a calculation device connected to a target device, the method comprising: identifying a contract identification code and obtaining a contract package file and a contract authentication code from at least one remote device; obtaining a microservice file corresponding to the target device from the remote device when a device embedded code of the calculation device is matching the contract authentication code; performing the microservice file to enable the target device according to the contract package file and generate an execution report; publishing the execution report to the remote device to obtain an acceptance certification code; and combining and hashing the device embedded code, the contract authentication code and the acceptance certification code to generate a hash value, and sending the hash value to a blockchain.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 23, 2024
    Inventors: Min-Hao LI, Yu-Chiao WANG, Ya-Ping LEE, Wei-Der CHUNG, Jhy-Ping WU
  • Publication number: 20240169100
    Abstract: A machine learning attack resistant strong PUF with a dual-edge sampling function comprises switch units, a first arbiter and a second arbiter. The first arbiter is for determining a sequential order of delays at a rising edge of signals input to a first input terminal and a second input terminal of the first arbiter. The second arbiter is for determining a sequential order of delays at a falling edge of signals input to a first input terminal and a second input terminal of the second arbiter. Each switch unit is composed of eight MOS transistors. The strong PUF has a high capacity to resist machine learning attacks and small hardware expenditure through simple structural design of the switch units, realizing machine learning attack resistance and small hardware expenditure at the same time, and generating a large number of challenge response pairs through dual-edge sampling realized by the two arbiters.
    Type: Application
    Filed: March 7, 2023
    Publication date: May 23, 2024
    Applicant: Wenzhou University
    Inventors: Gang LI, Hui Li, Pengjun WANG, Xilong Shao, Hao Ye