Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.

Abstract: A semiconductor device includes first channel members, a first gate structure wrapping around each of the first channel members, a first epitaxial feature abutting the first channel members, second channel members, a second gate structure wrapping around each of the second channel members, a second epitaxial feature abutting the second channel members, and an isolation feature has a first portion laterally stacked between the first and second gate structures and a second portion laterally stacked between the first and second epitaxial features. A width of the first portion of the isolation feature is larger than a width of the second portion of the isolation feature.

Abstract: A diode structure includes a nanosheet structure on a substrate, including a first, first-type diffusion region, a second, first-type diffusion region on the substrate, a first, second-type diffusion region, and a second, second-type diffusion region, each on the substrate. The diode structure includes a first gate on the nanosheet structure between the first and second, first-type diffusion regions. The diode structure includes a first frontside zero (M0) metal layer coupled to a frontside of the first and second, first-type diffusion regions, and a first backside M0 metal layer coupled to a backside of the first and second, first-type diffusion regions to form an anode. The diode structure includes a second frontside M0 metal layer coupled to a frontside of the first and second, second-type diffusion regions, and a second backside M0 metal layer coupled to a backside of the first and second, second-type diffusion regions to form a cathode.

Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.

Abstract: Disclosed are displacement sensors constructed from optical fibers having a long elongation with low-cost ToF sensors that advantageously do not suffer the infirmities of the art. The ToF sensor and the optical fiber ends that launch and receive light are packaged such that no ambient light affects measurements, and the structure is protected from contamination which eliminates optical degradation. With multi-point measurement capabilities and the low-cost features of ToF sensors, many displacement sensors can be arranged in a mesh to map out displacements over a large area and over all directions for civil and/or geotechnical structures. Wireless or other communications mechanisms may be employed in conjunction with our novel sensors to send real time measurement data to a central office for real time monitoring and analysis.

Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.

Abstract: Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: A controlling method for semiconductor process auxiliary apparatus, a control assembly and a manufacturing system are provided. The controlling method includes the following steps. At least one manufacturing parameter of a semiconductor manufacturing processing apparatus are obtained. An energy adjusting signal is generated according to the manufacturing parameter. An auxiliary apparatus controlling signal is generated according to the energy adjusting signal. The semiconductor process auxiliary apparatus is controlled according to the semiconductor auxiliary apparatus controlling signal.

Abstract: Provided is a sensing and adaptation method for exercise. The method is applied to a sensing and adaptation device for exercise and includes the following steps: generating an exercise game and a first resistance setting to an exercise equipment according to a first exercise target data; receiving an exercise interactive data of a user operating the exercise game from the exercise equipment; generating a reaction-time data according to a stage data of the exercise game and the exercise interactive data and generating an operation trajectory data according to the first resistance setting, the stage data and the exercise interactive data; calculating a deviation degree of the operation trajectory data; calculating a second exercise target data according to the deviation degree; generating a second resistance setting and updating the exercise game according to the second exercise target, and transmitting the second resistance setting to the exercise equipment.

Abstract: A semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. The semiconductor channel region is over a substrate. The source/drain region is adjacent the semiconductor channel region. The source/drain region has a notched corner. The contact structure has a portion inlaid in the notched corner in the source/drain region.

Abstract: A method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Abstract: A semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. The source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. The channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. Each of the at least one effective channel layer extends between the source/drain regions. Each of the at least one dummy channel layer extends between the isolation elements. The at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. The gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.

Abstract: A semiconductor device is provided. The semiconductor device includes a silicon layer over a fin, a doped semiconductor layer over the fin and adjoining the silicon layer, a plurality of channel layers over the silicon layer, a source/drain structure on the doped semiconductor layer and adjoining plurality of channel layers, and a plurality of inner spacers between the plurality of channel layers.

Abstract: A Reliability, Availability and Serviceability (RAS) offload Post-Package Repair (PPR) request system includes a memory system coupled to a Baseboard Management Controller (BMC) device and a Basic Input/Output System (BIOS) subsystem. The BMC device identifies an error in the memory system, retrieves error information associated with the error, uses the error information to generate a Post-Package Repair (PPR) request, and stores the PPR request in a BMC database provided in the BMC device. During an initialization process that occurs subsequent to storing the PPR request in the BMC database, the BMC device retrieves the PPR request and stores it in a shared buffer subsystem. During the initialization process, the BIOS retrieves the PPR request from the shared buffer subsystem, stores the PPR request in a BIOS database provided in the BIOS subsystem, and performs PPR operations on the memory system based on the PPR request stored in the BIOS database.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: A method of preparing a thermoplastic roofing membrane, the method comprising (i) extruding a composition including a thermoplastic polymer and a mineral filler to form an extrudate; (ii) forming the extrudate into a sheet having first and second planar surfaces; (iii) allowing the sheet to at least partially cool; and (iv) mechanically treating the first planar surface of the sheet to thereby expose the mineral filler.