Abstract: An apparatus for cleaning a package device is provided. The apparatus includes a package device loader; a package device unloader; a first cleaning area disposed between the package device loader and the package device unloader; and a conveyor. The conveyor includes a frame extending from the package device loader to the package device unloader and through the first cleaning area; and a belt wrapping the frame, wherein the belt includes a movable upper surface between the package device loader and the package device unloader, wherein the movable upper surface is configured to move relative to and over the frame, and a first distance between the movable upper surface and the frame in the first cleaning area increases in a direction from the package device loader to the package device unloader.

Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.

Abstract: Provided are indole alkaloid compounds in a noni enzyme, wherein the structural formula is shown in the following formula: Provided is a preparation method of the above-mentioned compound and application of the indole alkaloid compound in the noni enzyme in the preparation of an ?-glucosidase inhibitor. The indole alkaloid compound in the noni enzyme provided by the invention has a simple preparation process, low cost and abundant raw material sources.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: Immersion-type heat dissipating device thermally coupled to heat source includes heat conductor and boiling enhancement layer. The heat conductor includes a plurality of fin portions and a base portion, which is thermally coupled to the heat source and has heat receiving surface and heat dissipating surface opposite to each other. The fin portions protrude from the heat dissipating surface of the base portion. The boiling enhancement layer, which is disposed on at least part of the heat dissipating surface and at least part of the fin portions, includes at least one first metal portion and at least one second metal portion. A specific surface area of the at least one first metal portion is larger than a specific surface area of the at least one second metal portion.

Abstract: A method includes forming integrated circuit devices on a semiconductor substrate of a wafer, forming a voltage regulator in the wafer, and forming a metal layer as a part of the wafer. A transistor is formed farther away from the semiconductor substrate than the metal layer. The transistor includes a first source/drain region connected to the voltage regulator, and the voltage regulator is configured to convert a first voltage received from the first source/drain region to a second voltage that is lower than the first voltage, and provide the second voltage to the integrated circuit devices. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Abstract: A device includes a channel region, a gate structure, first and second gate spacers, and first and second dielectric liners. The gate structure is over the channel region. The epitaxial structure interfaces a sidewall of the channel region. An inner sidewall of the first gate spacer has a lower region interfacing a first side of the gate structure. An inner sidewall of the second gate spacer has a lower region interfacing a second side of the gate structure. A first dielectric liner interfaces an upper region of the inner sidewall of the first gate spacer. A second dielectric liner interfaces an upper region of the inner sidewall of the second gate spacer. The second dielectric liner is separated from the first dielectric liner in a cross-sectional view.

Abstract: A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub-arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a first metal gate layer for the P-type transistors and a second metal gate layer for the N-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistors.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: The present disclosure discloses an energy storage system and an information transmission apparatus for same. The information transmission apparatus for the energy storage system includes a plurality of device data collection terminals and a display terminal. Each of the plurality of device data collection terminals is adapted to be connected to one energy storage device. The display terminal is configured to perform wireless communication with the plurality of device data collection terminals. The device data collection terminal is configured to store a device query instruction to obtain, based on the device query instruction, device data from an energy storage device corresponding to the device data collection terminal, and to transmit the device data to the display terminal in response to receiving a data query instruction transmitted by the display terminal. The display terminal is configured to display the device data.

Abstract: A method and apparatus for evaluating vulnerability of monopile foundations of offshore wind turbines are provided. The method includes collecting offshore wind farm location data and wind-wave characteristic data, and simulating a wind-wave time course according to the offshore wind farm location data and the wind-wave characteristic data; determining a wind-wave dynamic load based on the wind-wave course; obtaining lateral soil resistance data of monopile foundations with a plurality of rock-soil strength parameters, and inputting the wind-wave dynamic load into a 3D finite element model; using the lateral soil resistance data of monopile foundations with a plurality of rock-soil strength parameters as boundary conditions of the 3D finite element model; and giving a limit state of monopile foundations, and determining vulnerability of monopile foundations on basis of the dynamic response result of the monopile foundations and the limit state of monopile foundations.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.