Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: Decoupled computing systems include layers of same-type computing resources, and include a dispatch layer to assign tasks from one layer to another, such as input and output (I/O) flows. The I/O flows can be assigned to particular computing resources of a layer based on a weighted moving average of performance data for the layer. When traffic is high, the assignment can include random assignment to some or all of the computing resources in the layer. The I/O flows can be split between read-intensive and write-intensive flows, with more read-intensive flows being assigned based on a pick ratio.

Abstract: Disclosed herein is a genetically engineered mesenchymal stem cells (MSC) comprising genetic alterations that increase gene expressions for adipogenic differentiation, mitochondrial biogenesis and a brown adipocyte marker. Also disclosed herein is a pharmaceutical composition and use of the pharmaceutical composition for preventing, ameliorating and/or treating a metabolic disorder.

Abstract: A method for manufacturing a semiconductor structure includes: forming stacks each including a first nanosheet layer and a second nanosheet layer; forming isolation features among the stacks; performing an ion implantation process such that top portions of the isolation features are formed into isolation protection elements; forming a gate structure, each of the stacks having two portions that are located at two opposite sides of the gate structure; removing the two portions of each of the stacks to form source/drain recesses such that the first nanosheet layer, the second nanosheet layer, and the stacks are respectively formed into a first nanosheet, a second nanosheet, and patterned stacks; forming source/drain portions respectively in the source/drain recesses; removing a dummy gate of the gate structure; removing the second nanosheet of each of the patterned stacks; and forming a gate electrode around the first nanosheet of each of the patterned stacks.

Abstract: Approaches for providing a non-disruptive file move are disclosed. A request to move a target file from the first constituent to the second constituent is received. The file has an associated file handle. The target file in the first constituent is converted to a multipart file in the first constituent with a file location for the new file in the first constituent. A new file is created in the second constituent. Contents of the target file are moved to a new file on the second constituent while maintaining access via the associated file handle via access to the multipart file. The target file is deleted from the first constituent.

Abstract: A method includes forming a package component, the package component comprising an integrated circuit die, attaching the package component to a package substrate; placing a heat spreader over the package component and the package substrate to form an integrated circuit package, wherein a height of the integrated circuit package is in a range from 2.5 mm to 6 mm, and performing a first automatic optical inspection (AOI) process on the integrated circuit package using an AOI apparatus to determine if the orientation and alignment of the heat spreader with regards to the package substrate is within specification, wherein the AOI apparatus comprises a lens that has a maximum depth of field that is greater than the height of the integrated circuit package, and wherein during the first AOI process the depth of field encompasses an entirety of the height of the integrated circuit package.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: Fully automatic welding forming equipment for a special-shaped three-dimensional workpiece and a welding method is provided. The welding forming equipment includes a base station, a welding robot, a displacement worktable, an auxiliary robot, and a hopper. The welding robot, the auxiliary robot and the hopper are arranged on the base station, and the displacement worktable is arranged between the base stations. The displacement worktable adopts the structure of main and sub double frames and main and sub double rotary power, which has multiple degrees of freedom, and can flexibly adjust the position and angle of the welded parts, realize the welding requirements of any position and angle, and meet the welding operation requirements of complex special-shaped three-dimensional components without manual repair welding operation, and the multi-point welding can be realized through the cooperation of welding robot and auxiliary robot to improve the welding efficiency and quality.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment of the present disclosure includes forming a plurality of semiconductor nanostructures vertically stacked above a substrate, forming a dielectric structure suspended above a topmost one of the semiconductor nanostructures, forming a plurality of inner spacers interleaving the semiconductor nanostructures, forming an epitaxial feature abutting the semiconductor nanostructures, and forming a gate structure wrapping around each of the semiconductor nanostructures and the dielectric structure.

Abstract: A rotary translational positioner with multiple degrees of freedom includes support frames, a main rotary dynamic structure, a main frame, an auxiliary dynamic structure, an auxiliary frame, and a worktable, where the main frame is arranged between the support frames, the main rotary dynamic structure is arranged at the end of the main frame and is located between the main frame and the support frame, the auxiliary frame is arranged in the main frame through the auxiliary dynamic structure, the auxiliary dynamic structure is arranged at the front end and the rear end of the auxiliary frame, and the worktable is arranged on the auxiliary frame. A main and auxiliary double frame structure is adopted, the main frame can adjust the position and angle of the whole welding workpiece, and the auxiliary frame can adjust the position and angle of the welding parts.

Abstract: A semiconductor structure includes a plurality of nanosheets, a gate structure, an S/D structure, a stepped structure, and a sidewall spacer. The plurality of nanosheets is disposed over a substrate, wherein the substrate extends along a first direction, and the nanosheets are arranged along a second direction substantially perpendicular to the first direction. The gate structure is disposed over the substrate, wherein the gate structure is disposed between and surrounding the nanosheets. The S/D structure is disposed adjacent to the gate structure and the plurality of nanosheets. The stepped structure is disposed below the S/D structure, wherein the stepped structure overlaps at least one of the nanosheets along the first direction. The sidewall spacer is disposed between the stepped structure and the at least one of the nanosheets. A method of manufacturing the semiconductor structure is also provided.

Abstract: Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.

Abstract: Provided are methods for side link communication, terminal devices, and network devices. A method comprises: according to a target candidate starting symbol, a terminal device determines in a first time slot symbols used for measuring a sidelink received signal strength indicator (SL RSSI). The symbol in the first time slot used for measuring the SL RSSI can be determined on the basis of the condition of candidate starting symbols.

Abstract: A method for predicting and controlling a water level of a series water conveyance canal on the basis of a fuzzy neural network is disclosed. The method includes: performing the relationship between a sluice opening degree and an open canal control water level by means of a fuzzy neural network, and constructing an upstream water level controller of a coupled predictive control algorithm; solving an optimal control rate of the upstream water level controller using a gradient optimization algorithm on the basis of a control target of the upstream water level controller; and generating a control strategy by collecting actually measured water level change information and multiplying the actually measured water level change information by the optimal control rate on the basis of the solved optimal control rate, thereby fulfilling the object of predicting and controlling the water level.

Abstract: A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Abstract: A semiconductor device structure includes a source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the S/D feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the S/D feature, a front side S/D contact in contact with the first silicide layer, a back side S/D contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ILD) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ILD and the gate dielectric layer.

Abstract: In a method for improving converter and compiler operator granularity, a processor extracts an operator granularity from an artificial intelligence framework and an original model. A processor receives device characteristics from a target device. A processor outputs a converter granularity level to a converter based on the operator granularity and the device characteristics. A processor outputs a compiler granularity level to a compiler based on the operator granularity and the device characteristics.