Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

Abstract: The present disclosure provides a video processing method, including: determining, according to a consulting message, a target short video corresponding to the consulting message; and pushing the target short video to a terminal sending the consulting message. The present disclosure further provides a live streaming processing method, an electronic apparatus, a live streaming system, a terminal, and a computer-readable storage medium. The video processing method can improve the user experience during a live streaming process.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: The disclosure provides a solar device. The solar device includes: a solar panel, having a first surface and a second surface arranged oppositely; and a support assembly, used to support the solar panel, herein the support assembly includes a support base and a support rod, the support base is arranged on the second surface, the support base is provided with an upper mounting hole and a lower mounting hole, the upper mounting hole and the lower mounting hole are arranged on the support base at intervals along a vertical direction, and the support rod may be selectively connected with the upper mounting hole or the lower mounting hole to adjust the inclination angle of the solar panel. Through a technical scheme provided by this disclosure, problems in an existing technology that the transportation is inconvenient and the power generation efficiency is low may be solved.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: This disclosure relates to a video cropping method and apparatus, storage medium, and electronic device. The present disclosure method: acquiring an original video to be cropped; performing frame extraction processing on the original video to obtain a plurality of target video frames; determining, for each of the target video frames, a target candidate cropping box corresponding to the target video frame according to a main content in the target video frame; performing interpolation processing according to the target candidate cropping box corresponding to each of the target video frames to determine a target cropping box corresponding to each frame picture in the original video; and cropping the original video according to the target cropping box corresponding to the each frame picture.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: Provided are a photovoltaic mount and a photovoltaic apparatus including the photovoltaic mount. The photovoltaic mount includes a support structure, a first deflection structure, a second deflection structure, and a space truss structure. The first deflection structure is rotatably connected to the support structure by a first rotation shaft. The second deflection structure is rotatably connected to the first deflection structure by a second rotation shaft. An extending direction of the second rotation shaft is different from an extending direction of the first rotation shaft. The space truss structure is installed on the second deflection structure and configured to carry a photovoltaic panel. The space truss structure is driven through a rotation of the first deflection structure and/or a rotation of the second deflection structure to deflect to change an installing angle of the photovoltaic panel.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.

Abstract: Disclosed are a method and device for realizing advanced nitrogen removal of mature landfill leachate and sludge reduction by using sludge fermentation products as carbon source, belonging to the field of biological treatment of sludge of high ammonia nitrogen wastewater.

Abstract: Embodiments of the present disclosure provide an information processing method and apparatus, and a device, the method includes: sending an information request to a platform side at a preset time interval if it is determined that a merchant platform application has been logged in; receiving a system message sent by the platform side in response to the information request in real time, where the system message is sent by a service side to the platform side in real time; and displaying the system message and/or prompt information of the system message on the merchant platform application. This embodiment does not require the merchant to obtain a new system message by refreshing a page, avoiding a repeated refresh operation by the merchant and avoiding the merchant missing an important notification due to not being able to obtain the system message in time.

Abstract: A single-stage multi-path direct current access converter and a control method thereof are provided. The single-stage multi-path direct current access converter includes an AC-side conversion circuit; at least two DC-side conversion circuits; and transformers corresponding to the at least two DC-side conversion circuits. AC sides of the at least two DC-side conversion circuits are respectively connected to primary windings of the corresponding transformers; secondary windings of the transformers are connected in parallel to a first side of the AC-side conversion circuit; each of the at least two DC-side conversion circuits is configured to invert DC power received by the DC-side conversion circuit, or to rectify AC power received by the DC-side conversion circuit; and the AC-side conversion circuit is configured to perform AC frequency conversion.

Abstract: A circuit board structure is provided. The circuit board structure includes a via hole, a conductive layer, and an alternate stacking of a plurality of circuit layers and a plurality of insulating layers. The via hole penetrates through the plurality of circuit layers and the plurality of insulating layers. The lateral ends of the plurality of insulating layers form the sidewall of the via hole. The conductive layer is conformally disposed within the via hole. The conductive layer exposes the first region of the sidewall and covers the second region of the sidewall. The sidewall extends in the longitudinal direction of the via hole and has no misalignments in the radial direction.

Abstract: An intelligent orthopedic external fixing system based on a cloud platform, includes a cloud platform, an intelligent recognition unit and a Taylor spatial frame manufacturing module, wherein the intelligent recognition unit comprises an osteotrauma reconstruction module, a three-dimensional medical model registration module, a condition characteristic extraction module, an image recognition module, a personalized designed module and a basic module. According to the disclosure, the cloud platform integrates medical registration technology, computer image recognition technology, three-dimensional reconstruction technology and deep machine learning technology.