Abstract: In a method for improving converter and compiler operator granularity, a processor extracts an operator granularity from an artificial intelligence framework and an original model. A processor receives device characteristics from a target device. A processor outputs a converter granularity level to a converter based on the operator granularity and the device characteristics. A processor outputs a compiler granularity level to a compiler based on the operator granularity and the device characteristics.

Abstract: An automatic pushing type complementary food device which includes a clamping body, an elastic member and a colander, wherein the inner side of the clamping body is connected to one end of an elastic member in a clamped manner, the outer side of the clamping body is connected to the colander in a clamped manner, the other end of the elastic member extends into the colander, a complementary food cavity is provided in the colander, and overflow holes are provided in the outer wall of the colander.

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

Abstract: A holding mechanism is provided, and includes a frame, a carrier, and a bracket. The frame is used to accommodate an electronic component. The carrier is affixed to the frame. The bracket has a sliding rail. The carrier is connected to the bracket via the sliding rail so that the frame may be rotated relative to the frame. Accordingly, additional electronic components can be disposed above the chassis, and the convenience of installing or removing electronic components can be improved.

Abstract: Disclosed are a main unit of ventilation device, a ventilation device, and a medical device, including a housing, a gas path assembly and a pressure monitoring assembly. The housing is provided with an inner cavity and an outer side of the housing is recessed inward to form an accommodating cavity. The gas path assembly includes an oxygen control assembly and an output interface. The oxygen control assembly is connected with an oxygen supply apparatus, the output interface is connected with an inspiratory branch. the accommodation cavity is configured to removably accommodate at least one portable medical device. The portable medical device includes an interface side which is provided with a cable interface, wherein when the portable medical device is accommodated inside the accommodation cavity, the output interface and the cable interface are located on different sides of the housing, so as to expand its function and broaden a use scope.

Abstract: A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor fin over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, first and second dielectric layers over the substrate, and an S/D contact disposed on the epitaxial S/D feature. The first and second dielectric layers have different material compositions. A first sidewall of the epitaxial S/D feature is facing the first dielectric layer, a second sidewall of the epitaxial S/D feature is facing the second dielectric layer, and the S/D contact partially covers a top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature.

Abstract: A data transmission control method is performed by a computer device that is wirelessly connected to a wireless access point, and the method includes: transmitting, to the wireless access point, a request frame carrying a target wake time (TWT) parameter, the TWT parameter comprising an indicator parameter for instructing the wireless access point to schedule the computer device to perform data transmission within a target wake time service period (TWT SP); receiving a response frame returned by the wireless access point; and transmitting, when the response frame indicates that the wireless access point confirms the TWT parameter, a data packet to the wireless access point within the TWT SP.

Abstract: This application is directed to systems, methods, and devices for image based analysis of plaque. In some embodiments, the approaches herein can be used for developing treatment plans, which can include local treatment, systemic treatment, or both. In some embodiments, the approaches herein can be used for stent selection. In some embodiments, the approaches herein can be used for surgical planning, which can include robotic surgical planning. In some embodiments, the approaches herein can be used for image normalization. In some embodiments, the approaches herein can be used for identifying plaque calcification thresholds. In some embodiments, the approaches herein can be used for identifying thin cap fibroatheroma. In some embodiments, the approaches herein can be used for coronary artery tree reconstruction. Some embodiments are directed to coronary artery disease risk stratification.

Abstract: An electric-thermal integrated energy control method is provided. The method comprises predicting renewable energy and multivariate loads in an integrated energy system based on a pretrained SA-PSO-BP neural network; constructing an objective function of the integrated energy system, and adding power network constraints and heat network constraints for optimal scheduling; and obtaining an optimal solution of the objective function by means of a SA-PSO algorithm based on prediction results of the renewable energy and the multivariate loads, and controlling the integrated energy system according to the optimal solution of the objective function; wherein, a training process of the SA-PSO-BP neural network comprises: training a BP neural network by means of a feature training set, and iterating and updating weights and thresholds in the BP neural network in the training process by means of the SA-PSO algorithm to obtain the SA-PSO-BP neural network.

Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

Abstract: The present disclosure provides a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.

Abstract: A method with object pose estimation includes: obtaining an instance segmentation image and a normalized object coordinate space (NOCS) map by processing an input single-frame image using a deep neural network (DNN); obtaining a two-dimensional and three-dimensional (2D-3D) mapping relationship based on the instance segmentation image and the NOCS map; and determining a pose of an object instance in the input single-frame image based on the 2D-3D mapping relationship.

Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.

Abstract: A semiconductor structure includes first and second channel structures, an isolation structure, a gate structure, first and second epitaxial features, and a dielectric layer. The isolation structure is disposed between the first and second channel structures. A top surface of the isolation structure comprises a first portion adjacent the first channel structure and a second portion equidistant from the first channel structure and the second channel structure, wherein the first portion is higher than the second portion. The gate structure is disposed over the first and second channel structures. The first epitaxial feature is adjacent to a sidewall of the first channel structure. The second epitaxial feature is adjacent to a sidewall of the second channel structure. The dielectric layer is between the first channel structure and the second channel structure. The dielectric layer is over the second portion of the isolation structure and has a U-shaped cross-sectional profile.

Abstract: The present disclosure discloses a control method. The method includes: acquiring target operation state information of an output circuit of a transformer to determine an operation state of a power grid based on the target operation state information; and controlling a switching transistor in the output circuit and an input circuit of the transformer to reduce the target current in response to determining that the power grid is in a predetermined operation state.