Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.

Abstract: A method includes receiving a first data set comprising embeddings of first and second types, generating a fixed adjacency matrix from the first dataset, and applying a first stochastic binary mask to the fixed adjacency matrix to obtain a first subgraph of the fixed adjacency matrix. The method also includes processing the first subgraph through a first layer of a graph convolutional network (GCN) to obtain a first embedding matrix, and applying a second stochastic binary mask to the fixed adjacency matrix to obtain a second subgraph of the fixed adjacency matrix. The method includes processing the first embedding matrix and the second subgraph through a second layer of the GCN to obtain a second embedding matrix, and then determining a plurality of gradients of a loss function, and modifying the first stochastic binary mask and the second stochastic binary mask using at least one of the plurality of gradients.

Abstract: Various embodiments of the teachings herein include a method for deploying power quality monitoring (PQM) devices. The method may include: determining a maximum number of PQM devices and historical power data of candidate deployment points, wherein the number of the candidate deployment points is greater than the maximum number of the PQM devices; clustering the historical power data of the candidate deployment points, wherein a target number of categories is determined on the basis of a silhouette coefficient of each candidate number of categories and the maximum number of the PQM devices; and determining PQM device deployment points based on the center of each category in the target number of categories.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: A dielectric barrier discharging tube, which has a synergistic column of needle electrodes to utilize a plurality of channels to adsorb catalysts, is provided. The dielectric barrier discharging tube includes: a quartz tube, a high-voltage pole, an inner electrode, and a plurality discharging needle sets. Two catalytic blocks are arranged respectively on two sides of each set discharging needles. Each catalytic block defines at least one inclined inner channel and at least one inclined outer channel. A higher end of each channel faces towards the discharging needle, and a lower end of each channel faces towards the discharging needle.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.

Abstract: This application relates to compounds of Formula I: or pharmaceutically acceptable salts thereof, which are inhibitors of TAM kinases which are useful for the treatment of disorders such as cancer.

Abstract: Provided are transaminase mutants and uses thereof. The transaminase mutant is obtained by one or more amino acid mutations occurring in SEQ ID NO: 2 or is a mutant with a conserved amino acid mutation obtained by taking the sequence SEQ ID NO: 1 of a wild-type CvTA transaminase as a reference. Compared with wild-type transaminases, the catalytic activity of the mutant is improved to different degrees, so that the production efficiency of chiral amine compound synthesis may be improved.

Abstract: A method for comprehensively analyzing and/or evaluating cigarette burning quality index is disclosed. The steps include collecting cigarette burning quality index data, filtering the cigarette burning quality index data, standardizing cigarette data, and measuring cigarette burning quality. The importance of the cigarette burning quality indicators can also be evaluated. The method for comprehensively analyzing and/or evaluating cigarette burning quality indicators can reflect general laws more accurately by maintaining the sample distribution through a singularity detection method, and analyzing correlations of each index with cigarette performance from multiple perspectives, to fuse them into a comprehensive measurement value. The importance ranking and weight of indicators can be obtained more completely and stably.

Abstract: A dynamic interface layout method includes that a width of a screen of an electronic device is divided into a plurality of columns. The electronic device displays a first interface on the screen. After detecting an interface refresh signal, the electronic device obtains a first column quantity corresponding to a width of a second interface to be displayed after refreshing. The first column quantity is a quantity of columns included in the width of the second interface. The electronic device determines a second column quantity according to a layout rule corresponding to a first element on the second interface. The second column quantity is a quantity of columns included in a width of the first element. The electronic device displays the second interface on the screen.

Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.

Abstract: The present invention relates to a compound of formula (I) capable of inhibiting plasmin activity and having blood coagulation and hemostasis activity, and a pharmaceutically acceptable salt, hydrate, isomer, prodrug and mixture thereof, wherein R1 to R3 are as defined in the description.

Abstract: A system for use with a direct current fast-charging (DCFC) station includes a controller and battery system. The battery system includes first and second battery packs, and first, second, and third switches. The switches have ON/OFF conductive states commanded by the controller to connect the battery packs in a parallel-connected (P-connected) or series-connected (S-connected) configuration. An electric powertrain with one or more electric machines is powered via the battery system. First and second charge ports of the system are connectable to the station via a corresponding charging cable. The first charge port receives a low or high charging voltage from the station. The second charge port receives a low charging voltage. When the station can supply the high charging voltage to the first charge port, the controller establishes the S-connected configuration via the switches, and thereafter charges the battery system solely via the first charge port.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: An output circuit includes a comparator circuit, a voltage conversion circuit and a signal output circuit. The comparator circuit detects an operating mode based on a first supply voltage and a second supply voltage and generates a first control signal. The voltage conversion circuit adjusts a level of an output voltage from a low-dropout regulator according to the first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. The signal output circuit adjusts a level of a digital signal according to the first voltage, the second voltage and the first supply voltage to generate a digital output signal corresponding to the operating mode.

Abstract: A display module (10) includes: a display panel (12) and a circuit board (14) coupled to the display panel (12). The display panel (12) includes a driving chip (122) and a display unit (124); and the circuit board (14) includes a first filter element (142), wherein the first filter element (142) is coupled to the driving chip (122) and the display unit (124), and a direct current signal output by the driving chip (122) is filtered by the first filter element (142) and then transmitted to the display unit (124). The present disclosure also provides a display apparatus (100).

Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.