Abstract: The invention discloses a monoclonal antibody against human GPR48 and application of the same. In the antibody provided by the present invention, the amino acid sequences of LCDR1, LCDR2, and LCDR3 in the light chain variable region are shown in positions 27-32, 50-52, and 89-97 of SEQ ID No.1 sequentially, and the amino acid sequences of HCDR1, HCDR2 and HCDR3 in the heavy chain variable region are shown in positions 26-33, 51-60 and 99-108 of SEQ ID No.2 sequentially. The antibody has strong specificity and sensitivity to GPR48 protein, and can be applied to immunological experimental techniques such as western blotting, immunofluorescence and immunohistochemistry; it can be applied to flow cytometry experimental techniques such as flow cyometry analysis and flow cytometry sorting; it can be applied to the scientific research of signaling pathways such as subcellular localization and protein interaction.

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

Abstract: Wireless communication devices are adapted to facilitate a random access procedure. According to one example, scheduled entity can transmit a first transmission that is received by a scheduling entity. The first transmission may include a physical random access channel (PRACH) preamble sequence and a first message including information for determining a device-specific network identifier for the scheduled entity. The scheduling entity may transmit a second transmission that is received by the scheduled entity. The second transmission may include information on a physical downlink control channel (PDCCH) addressed to the device-specific network identifier for the scheduled entity, and a second message on a physical downlink shared channel (PDSCH). Other aspects, embodiments, and features are also included.

Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.

Abstract: Disclosed is a fluorescent PCR method for detecting HLA-B*15:02 allele and a specific primer probe combination. In the present disclosure, a set of primers and probes are designed based on an HLA-B*15:02 specific SNP gene locus by using TaqMan probe technology, combining another set of primers and probes corresponding to the internal reference gene ?-Actin, and a set of primer probe for non-HLA-B*15:02 genes are designed to detect whether a DNA sample contains an HLA-B*15:02 gene and whether a sample is homozygous or heterozygous. Compared with the similar detection methods in the past, the technical scheme in the present disclosure inherits the advantages of high specificity, high throughput, high resolution, low cost, simple and convenient operation, process controllability and the like of the fluorescent PCR, and may detect whether a sample is homozygous or heterozygous.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: A series-parallel monorail hoist based on an oil-electric hybrid power and a controlling method thereof. The monorail hoist includes a cabin, a hydraulic driving system, a lifting beam, a gear track driving and energy storage system, and a speed adaptive control system connected in series with each other and travelling on a track. The monorail hoist is capable of implementing an independent drive by an electric motor or a diesel engine in an endurance mode, a hybrid drive of the electric motor and the diesel engine in a transportation mode, and a hybrid drive of the diesel engine and a flywheel energy storage system in a climbing mode, according to different operating conditions that include conditions of an upslope, a downslope and a load. Power requirements for the monorail hoist under various operating conditions are satisfied, and the excess energy is recovered during the process of travelling.

Abstract: A writing panel includes an array substrate, a flexible substrate disposed opposite to the array substrate, a liquid crystal layer disposed between the array substrate and the flexible substrate, and a plurality of spacers each in a shape of a column disposed on a surface of the array substrate proximate to the liquid crystal layer. The array substrate includes a base and a pixel driving circuit layer disposed on the base, and the pixel driving circuit layer includes a plurality of thin film transistors and a plurality of signal lines. An orthographic projection of each spacer on the base is non-overlapping with orthographic projections of the plurality of thin film transistors and the plurality of signal lines on the base.

Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.

Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.

Abstract: Provided are an esterase mutant and use thereof. The amino acid sequence of the esterase mutant has a sequence as shown in SEQ ID NO: 1, and sites at which amino acid mutations occur include an N51G site.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: Described are a method, system, and computer program product for generating robust graph neural networks using universal adversarial training. The method includes receiving a graph neural network (GNN) model and a bipartite graph including an adjacency matrix, initializing model parameters of the GNN model, initializing perturbation parameters, and sampling a subgraph of a complementary graph based on the bipartite graph. The method further includes repeating until convergence of the model parameters: drawing a random variable from a uniform distribution; generating a universal perturbation matrix based on the subgraph, the random variable, and the perturbation parameters; determining Bayesian Personalized Ranking (BPR) loss by inputting the bipartite graph and the universal perturbation matrix to the GNN model; updating the perturbation parameters based on stochastic gradient ascent; and updating the model parameters based on stochastic gradient descent.

Abstract: An end cover assembly, an air cylinder, a tread sweeper and a railway vehicle.