Patents by Inventor Hao Yu

Hao Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12148671
    Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Chia-Hao Yu, Hsiao Wen Lee
  • Publication number: 20240379822
    Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Bone-Fong Wu, Chih-Hao Yu, Chia-Pin Lin
  • Publication number: 20240379364
    Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
  • Patent number: 12143221
    Abstract: A method performed by a UE is provided. The method includes receiving DCI on a PDCCH from a BS, the DCI indicating a PDSCH; receiving a MAC CE command on the PDSCH; determining, according to the DCI, whether a HARQ ACK feedback for a data reception on the PDSCH is needed to be transmitted; and applying, after determining that the HARQ ACK feedback is needed to be transmitted, the MAC CE command after a first slot identified by a first value of n+K0+K1+Np+M, where n is an index of a slot in which the DCI is received, K0 and K1 are slot offsets, Np indicates an approximated delay determined by a TA value, and M indicates a processing delay.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: November 12, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Chien-Chun Cheng, Chia-Hao Yu, Hung-Chen Chen
  • Publication number: 20240372979
    Abstract: A display device includes a view generator for generating input view numbers according to positions of a viewer's eyes, a view curve modifier for generating output view numbers according to the input view numbers, a three dimensional (3D) image data sampling module for adjusting image data of pixels according to the output view numbers, and a display module for displaying at least one image according to the pixels and the image data, wherein viewing positions are modified by the view curve modifier to generate modified viewing positions, the viewing positions correspond to first views, the modified viewing positions correspond to second views, and a number of second views is smaller than a number of first views.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: InnoLux Corporation
    Inventors: Naoki SUMI, Hao-Yu Liou
  • Patent number: 12137447
    Abstract: A method for a UE for performing a HARQ feedback operation for an SPS transmission is disclosed.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 5, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Chia-Hao Yu, Chien-Chun Cheng, Chia-Hung Wei, Chie-Ming Chou
  • Publication number: 20240363483
    Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die disposed over a substrate, a first TIM layer over the first semiconductor die, a second TIM layer over the second semiconductor die, and an underfill between the substrate, the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output, and the second semiconductor die includes a second heat output less than the first heat output. The first TIM layer and the second TIM layer are in contact with the underfill. A thermal conductivity of the first TIM layer is greater than a thermal conductivity of the second TIM layer. An adhesion of the second TIM layer is greater than an adhesion of the first TIM layer. The first TIM layer is separated from the second TIM layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: TING-YU YEH, CHIA-HAO HSU, WEIMING CHRIS CHEN, KUO-CHIANG TING, TU-HAO YU, SHANG-YUN HOU
  • Publication number: 20240361355
    Abstract: A membrane probe card includes probes each having a base electrically connected with a trace of a membrane wiring structure, and a probe tip protruding from the base. The base has a tip placement section and an extension section, which extend from a first side edge to a second side edge of the base in order. The probe tip is made by laser processing and electroplating, located at the tip placement section, and provided with a fixed end portion connected with the base in a way that the width of the tip placement section is greater than the width of the fixed end portion. A distance from a center of the probe tip to the first side edge is less than a distance from the center of the probe tip to the second side edge. As such, requirements of fine pitch and probe height may be achieved.
    Type: Application
    Filed: April 17, 2024
    Publication date: October 31, 2024
    Applicant: MPI CORPORATION
    Inventors: YU-SHAN HU, SHAO-LUN WEI, YU-WEN WANG, HAO-YU CHUNG
  • Publication number: 20240363518
    Abstract: A semiconductor device includes a dielectric interposer, a first RDL, a second RDL, and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first RDL is disposed over the first surface of the dielectric interposer. The second RDL is disposed over the second surface of the dielectric interposer. The conductive structures are disposed through the dielectric interposer and directly contact the dielectric interposer. The conductive structures are electrically connected to the first RDL and the second RDL. Each of the conductive structures has a tapered profile. A minimum width of each of the conductive structures is proximal to the first RDL, and a maximum width of each of the conductive structures is proximal to the second RDL.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: KUO-CHIANG TING, CHI-HSI WU, SHANG-YUN HOU, TU-HAO YU, CHIA-HAO HSU, PIN-TSO LIN, CHIA-HSIN CHEN
  • Patent number: 12130390
    Abstract: A LIDAR-to-vehicle alignment system includes a memory and alignment and autonomous driving modules. The memory stores points of data provided based on an output of one or more LIDAR sensors and localization data. The alignment module performs an alignment process including: based on the localization data; determining whether a host vehicle is turning; in response to the host vehicle turning; selecting a portion of the points of data; aggregating the selected portion to provide aggregated data; selecting targets based on the aggregated data; and based on the selected targets, iteratively reducing a loss value of a loss function to provide a resultant LIDAR-to-vehicle transformation matrix. The autonomous driving module: based on the resultant LIDAR-to-vehicle transformation matrix, converts at least the selected portion to at least one of vehicle coordinates or world coordinates to provide resultant data; and performs one or more autonomous driving operations based on the resultant data.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: October 29, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Xinyu Du, Yao Hu, Wende Zhang, Hao Yu
  • Patent number: 12124178
    Abstract: A system is provided. The system includes an exposing device configured to generate a real-time image, including multiple first align marks, of a mask and an adjusting device configured to adjust an off-set of the mask from a pre-determined position to be smaller than a minimum aligning distance according to the first align marks and multiple align marks on a substrate, and further to move the mask closer to the pre-determined position to have a displacement, less than a minimum mapping distance, from the pre-determined position according to the real-time image and a reference image of the mask.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Yu Lan, Po-Chung Cheng, Ching-Juinn Huang, Tzung-Chi Fu, Tsung-Yen Lee
  • Publication number: 20240345733
    Abstract: Methods, systems, and devices for checkpoint procedure detection and latency reduction are described. A memory system may determine that a checkpoint procedure has been initiated. Based on determining that the checkpoint procedure has been initiated, the memory system may write metadata associated with the checkpoint procedure to a non-volatile memory using a first type of write operation that has lower latency than a second type of write operation supported by the non-volatile memory. The memory system may also write checkpoint information about the metadata to the non-volatile memory using the first type of write operation.
    Type: Application
    Filed: April 8, 2024
    Publication date: October 17, 2024
    Inventors: Yanhua Bi, Luca Porzio, Hao Yu
  • Publication number: 20240349183
    Abstract: A method for a base station (BS) instructing a UE to monitor a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises transmitting a discontinuous reception (DRX) configuration to the UE indicating to monitor a scheduling signal on the PDCCH within a DRX active time, and transmitting a configuration to the UE for monitoring the power saving signaling on the PDCCH, instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.
    Type: Application
    Filed: April 23, 2024
    Publication date: October 17, 2024
    Inventors: Yu-Hsin Cheng, Hsin-Hsi Tsai, Chia-Hao Yu, Chie-Ming Chou
  • Publication number: 20240348295
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus implements a user equipment (UE) node representing a UE in a cell-free multiple-input multiple-output (MIMO) network. The UE node receives a plurality of probability estimates for a plurality of possible symbols transmitted by the UE from a plurality of access point (AP) nodes. The UE node aggregates the plurality of probability estimates from the plurality of AP nodes to obtain a system-level probability estimate. The UE node generates an updated plurality of probability estimates for the plurality of possible symbols based on the system-level probability estimate. The UE node transmits the updated plurality of probability estimates to the plurality of AP nodes.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 17, 2024
    Inventors: Ti-Yu Chen, Tzi-Dar Chiueh, Chia-Hao Yu
  • Publication number: 20240345732
    Abstract: Methods, systems, and devices for detection and latency reduction of write-intensive procedures in a memory system are described. A memory system may determine that a set of write commands share a group identifier associated with a writeback procedure or target a swap area of the non-volatile memory associated with a swap procedure. The memory system may determine that the writeback procedure or the swap procedure has been. The memory system may write, based on determining that the writeback procedure or the swap procedure has been initiated, data associated with the set of write commands to the non-volatile memory using a first type of write operation that has lower latency than a second type of write operation.
    Type: Application
    Filed: April 2, 2024
    Publication date: October 17, 2024
    Inventors: Yanhua Bi, Luca Porzio, Hao Yu
  • Publication number: 20240347624
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Inventors: Jin-Mu Yin, Wei-Yang Lee, Chih-Hao Yu, Yen-Ting Chen, Chia-Pin Lin
  • Patent number: 12120848
    Abstract: A cooling module includes: a fan having a fan housing with an intake port and an exhaust port; a fin that faces the exhaust port of the fan; a heat pipe connected to a surface of the fin; and a plate-shaped vapor chamber having a first surface and a second surface, the heat pipe being connected to the first surface while straddling one edge of the vapor chamber, the second surface at the one edge being connected to the surface of the fin to be parallel with the heat pipe, so that the one edge is disposed between the heat pipe and the fin.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: October 15, 2024
    Assignee: LENOVO (SINGAPORE) PTE. LTD.
    Inventors: Hao-Yu Wang, Akinori Uchino, Hajime Yoshizawa, Shusaku Tomizawa
  • Patent number: 12119117
    Abstract: This disclosure discloses a method and system for predicting disease quantification parameters for an anatomical structure. The method includes extracting a centerline structure based on a medical image. The method further includes predicting the disease quantification parameter for each sampling point on the extracted centerline structure by using a GNN, with each node corresponds to a sampling point on the extracted centerline structure and each edge corresponds to a spatial constraint relationship between the sampling points. For each node, a local feature is extracted based on the image patch for the corresponding sampling point by using a local feature encoder, and a global feature is extracted by using a global feature encoder based on a set of image patches for a set of sampling points, which include the corresponding sampling point and have a spatial constraint relationship defined by the centerline structure.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: October 15, 2024
    Assignee: SHENZHEN KEYA MEDICAL TECHNOLOGY CORPORATION
    Inventors: Xin Wang, Youbing Yin, Bin Kong, Yi Lu, Hao-Yu Yang, Xinyu Guo, Qi Song
  • Publication number: 20240339544
    Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
  • Patent number: 12112506
    Abstract: A system for determining calibrated camera extrinsic parameters for an autonomous vehicle includes a camera mounted to the autonomous vehicle collecting image data including a plurality of image frames. The system also includes one or more automated driving controllers in electronic communication with the camera that executes instructions to determine a vehicle pose estimate based on position and movement of the autonomous vehicle by a localization algorithm. The one or more automated driving controllers determine the calibrated camera extrinsic parameters based on three dimensional coordinates for specific feature points of interests corresponding to two sequential image frames, the specific feature points of interests corresponding to the two sequential image frames, and the camera pose corresponding to the two sequential image frames.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 8, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Farui Peng, Hao Yu