Patents by Inventor Haruki Ito

Haruki Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060131721
    Abstract: A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having a thickness greater than a height of a portion of the feedthrough electrode that projects from the active surface, and having an opening portion for exposing at least a portion of the feedthrough electrode; a wiring layer which is formed on the first resin layer, and which is connected to the feedthrough electrode through the opening portion; and an external connecting terminal connected to the wiring layer.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 22, 2006
    Inventor: Haruki Ito
  • Publication number: 20060055013
    Abstract: An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.
    Type: Application
    Filed: August 15, 2005
    Publication date: March 16, 2006
    Inventors: Haruki Ito, Nobuaki Hashimoto
  • Publication number: 20060049840
    Abstract: A test probe having a conductive part electrically connected to terminals of a test-object device, including: a silicon substrate; a protrusion made of resin provided on the silicon substrate; a first conductive part which is provided on the protrusion and comes in contact with the terminals; and a second conductive part which is provided in a region other than a region having the protrusion on the silicon substrate and is electrically connected to the first conductive part.
    Type: Application
    Filed: July 19, 2005
    Publication date: March 9, 2006
    Inventors: Haruki Ito, Shinji Mizuno, Koji Yamaguchi
  • Publication number: 20050275115
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Application
    Filed: May 13, 2005
    Publication date: December 15, 2005
    Inventors: Shuichi Tanaka, Haruki Ito, Yasuhito Aruga, Ryohei Tamura, Michiyoshi Takano
  • Publication number: 20050205296
    Abstract: A panel for an electro-optical apparatus, includes a substrate, a plurality of wires formed on the substrate, convex portions formed from resin and provided either on the plurality of wires or on the substrate, conductive layers provided so as to cover at least a portion of the surfaces of the convex portions, and that are electrically connected to the respective wires, and a plurality of external connection terminals for electrically connecting electronic components, formed by the convex portions and the conductive layers.
    Type: Application
    Filed: March 4, 2005
    Publication date: September 22, 2005
    Inventor: Haruki Ito
  • Patent number: 6940160
    Abstract: A semiconductor device comprising: a semiconductor element (10) having a plurality of electrodes (12); an interconnect pattern (20) electrically connected to the electrodes (12); a plurality of laminated insulating layers (41, 42 and 43); and a plurality of external terminals (30) electrically connected to the interconnect pattern (20). A plurality of holes (44, 46, and 48) are respectively formed in the insulating layers (41, 42, and 43) to form an opening portion (40) communicating from the hole (48) in the highest insulating layer (43) to the hole (44) in the lowest insulating layer (41). An external terminal (30) is provided within the opening portion (40), and the second hole (46) formed in the higher positioned second insulating layer (42) is larger than the first hole (44) formed in the lower positioned first insulating layer (41).
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: September 6, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Terunao Hanaoka, Haruki Ito, Kazuhiko Nozawa
  • Publication number: 20050170602
    Abstract: A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.
    Type: Application
    Filed: April 5, 2005
    Publication date: August 4, 2005
    Inventor: Haruki Ito
  • Publication number: 20050133914
    Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 23, 2005
    Inventor: Haruki Ito
  • Publication number: 20050133937
    Abstract: A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; a plurality of resin layers; a plurality of wirings; and a plurality of external terminals coupled to the wirings. First wirings of the plural wirings are formed at the bottom of a first resin layer and second wirings are formed at the top of the first resin layer.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 23, 2005
    Inventor: Haruki Ito
  • Patent number: 6852621
    Abstract: A method of manufacturing a semiconductor device comprises a step of forming a through-hole in a semiconductor chip having an electrode and forming a conductive layer on a region comprising an inner side of the through-hole. An intermediate portion of the through-hole is formed to be larger than an edge portion thereof, and the conductive layer is formed by electroless plating.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: February 8, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Terunao Hanaoka, Kenji Wada, Nobuaki Hashimoto, Haruki Ito, Kazushige Umetsu, Fumiaki Matsushima
  • Publication number: 20040192024
    Abstract: A resin layer is formed on a semiconductor substrate in which a plurality of integrated circuits are formed. In the surface of the resin layer, a plurality of recesses are formed. On the resin layer, an interconnecting line is formed to pass along any of the recesses. The semiconductor substrate is cut into a plurality of semiconductor chips. Each recess is formed to have an opening width less than the thickness of the interconnecting line, and a depth of at least 1 &mgr;m.
    Type: Application
    Filed: January 21, 2004
    Publication date: September 30, 2004
    Inventor: Haruki Ito
  • Publication number: 20040145031
    Abstract: A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.
    Type: Application
    Filed: December 2, 2003
    Publication date: July 29, 2004
    Inventor: Haruki Ito
  • Publication number: 20040092099
    Abstract: A method of manufacturing a semiconductor device comprises a step of forming a through-hole in a semiconductor chip having an electrode and forming a conductive layer on a region comprising an inner side of the through-hole. An intermediate portion of the through-hole is formed to be larger than an edge portion thereof, and the conductive layer is formed by electroless plating.
    Type: Application
    Filed: November 3, 2003
    Publication date: May 13, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Terunao Hanaoka, Kenji Wada, Nobuaki Hashimoto, Haruki Ito, Kazushige Umetsu, Fumiaki Matsushima
  • Patent number: 6707153
    Abstract: A method of manufacturing a semiconductor device comprising a step of forming a plurality of resin layers, an interconnect connected electrically to an electrode of each of a plurality of semiconductor elements, and an external terminal connected electrically to the interconnect, on an aggregate of semiconductor elements having an electrode, and a step of cutting the aggregate, wherein at least one resin layer among the plurality of resin layers is formed avoiding a cutting region of the aggregate.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: March 16, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Keiji Kuwabara, Terunao Hanaoka, Haruki Ito
  • Patent number: 6667551
    Abstract: A method of manufacturing a semiconductor device comprises a step of forming a through-hole in a semiconductor chip having an electrode and forming a conductive layer on a region comprising an inner side of the through-hole. An intermediate portion of the through-hole is formed to be larger than an edge portion thereof, and the conductive layer is formed by electroless plating.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: December 23, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Terunao Hanaoka, Kenji Wada, Nobuaki Hashimoto, Haruki Ito, Kazushige Umetsu, Fumiaki Matsushima
  • Patent number: 6608371
    Abstract: A method of manufacturing a semiconductor device includes: a first step of forming a first through hole that penetrates the location of the electrode in a semiconductor element having an electrode; a second step of providing an insulating material in a region including an inside of the first through hole, in such a manner that a second through hole is provided penetrating through the insulating material; and a third step of providing a conductive member within the second through hole that penetrates through at least the insulating material in the inside of the first through hole.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: August 19, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yohei Kurashima, Kazushige Umetsu, Haruki Ito
  • Patent number: 6488788
    Abstract: A flat plate member with gear portion is formed to a predetermined shape by pressing a flat steel raw material having a composition comprising, by weight, 0.10-0.18% C, less than 0.03% Si, 0.60-1.50% Mn, less than 0.020% P, less than 0.013% S, 0.001-0.004% B and the balance Fe with inevitable impurities, wherein quenching is performed on only the gear portion.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: December 3, 2002
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Haruki Ito, Yukio Isomura, Naoyuki Yamada
  • Publication number: 20020017710
    Abstract: A method of manufacturing a semiconductor device includes: a first step of forming a first through hole that penetrates the location of the electrode in a semiconductor element having an electrode; a second step of providing an insulating material in a region including an inside of the first through hole 18, in such a manner that a second through hole is provided penetrating through the insulating material; and a third step of providing a conductive member within the second through hole that penetrates through at least the insulating material in the inside of the first through hole.
    Type: Application
    Filed: July 11, 2001
    Publication date: February 14, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yohei Kurashima, Kazushige Umetsu, Haruki Ito
  • Publication number: 20020014291
    Abstract: A flat plate member with gear portion is formed to a predetermined shape by pressing a flat steel raw material having a composition comprising, by weight, 0.10-0.18% C, less than 0.03% Si, 0.60-1.50% Mn, less than 0.020% P, less than 0.013% S, 0.001-0.004% B and the balance Fe with inevitable impurities, wherein quenching is performed on only the gear portion.
    Type: Application
    Filed: June 28, 2001
    Publication date: February 7, 2002
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Haruki Ito, Yukio Isomura, Naoyuki Yamada
  • Publication number: 20020008320
    Abstract: A method of manufacturing a semiconductor device comprising a step of forming a plurality of resin layers, an interconnect connected electrically to an electrode of each of a plurality of semiconductor elements, and an external terminal connected electrically to the interconnect, on an aggregate of semiconductor elements having an electrode, and a step of cutting the aggregate, wherein at least one resin layer among the plurality of resin layers is formed avoiding a cutting region of the aggregate.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 24, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Keiji Kuwabara, Terunao Hanaoka, Haruki Ito