Patents by Inventor Haruo Nakazawa

Haruo Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11264240
    Abstract: A semiconductor device is manufactured by implanting impurity ions in one surface of a semiconductor substrate made of silicon carbide; irradiating a region of the semiconductor substrate implanted with the impurity ions with laser light of a wavelength in the ultraviolet region; and forming, on a surface of a high-concentration impurity layer formed by irradiating with the laser light, an electrode made of metal in ohmic contact with the high-concentration impurity layer. When irradiating with the laser light, a first concentration peak of the impurity ions that exceeds a solubility limit concentration of the impurity ions in silicon carbide is formed in a surface region near the one surface of the semiconductor substrate within the high-concentration impurity layer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa
  • Patent number: 11245010
    Abstract: A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kosuke Yoshida, Haruo Nakazawa, Kenichi Iguchi, Koh Yoshikawa, Motoyoshi Kubouchi
  • Patent number: 11069779
    Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of silicon carbide, a device structure provided on top of the first semiconductor layer, a second semiconductor layer of silicon carbide having a higher impurity concentration than the first semiconductor layer, provided under the first semiconductor layer, the second semiconductor layer implementing an ohmic-contact, and a metallic electrode film provided under the second semiconductor layer. A thickness of a carbon-containing region in which carbon-atoms are precipitated between the second semiconductor layer and the metallic electrode film is 10 nm or less.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 20, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa, Yusuke Wada
  • Publication number: 20210111248
    Abstract: A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer.
    Type: Application
    Filed: September 3, 2020
    Publication date: April 15, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kosuke YOSHIDA, Haruo NAKAZAWA, Kenichi IGUCHI, Koh YOSHIKAWA, Motoyoshi KUBOUCHI
  • Patent number: 10727060
    Abstract: A doping system includes a light source to emit an optical pulse; a light source controller connected to the light source, to control an energy density of the optical pulse; and a beam adjusting unit to irradiate the optical pulse to a surface of a doping-object made of silicon carbide on which an impurity-containing source-film containing impurity atoms is deposited. The light source controller irradiates a first optical pulse to the impurity-containing source-film so as to form a reaction-product layer in the doping-object, and irradiates a second optical pulse having an energy density higher than an energy density of the first optical pulse, so as to introduce the impurity atoms into the target through the reaction-product layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa
  • Patent number: 10658183
    Abstract: An impurity-doping apparatus is provided with: a supporting plate which supports a semiconductor substrate; a wall-like block disposed above the supporting plate floating away from the semiconductor substrate, the wall-like block implements a recess inside so as to establish a space for a solution region containing impurity elements, the solution region is localized on an upper surface of the semiconductor substrate, the upper surface being opposite to an bottom surface facing to the supporting plate; and a laser optical system, configured to irradiate a laser beam onto the upper surface of the semiconductor substrate, through the solution region surrounded by the wall-like block, wherein the impurity elements are doped into a part of the semiconductor substrate by irradiation of the laser beam.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 19, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa, Masaaki Ogino
  • Publication number: 20200066528
    Abstract: A semiconductor device is manufactured by implanting impurity ions in one surface of a semiconductor substrate made of silicon carbide; irradiating a region of the semiconductor substrate implanted with the impurity ions with laser light of a wavelength in the ultraviolet region; and forming, on a surface of a high-concentration impurity layer formed by irradiating with the laser light, an electrode made of metal in ohmic contact with the high-concentration impurity layer. When irradiating with the laser light, a first concentration peak of the impurity ions that exceeds a solubility limit concentration of the impurity ions in silicon carbide is formed in a surface region near the one surface of the semiconductor substrate within the high-concentration impurity layer.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 27, 2020
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Kenichi IGUCHI, Haruo NAKAZAWA
  • Patent number: 10559664
    Abstract: A method of manufacturing a semiconductor device includes assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate where the epitaxial-growth layer is grown on a bulk layer and forming a plurality of device structures on the plurality of chip regions, respectively, thinning the semiconductor substrate from a bottom-surface side of the bulk layer, bonding a supporting-substrate on a bottom surface of the thinned semiconductor substrate, selectively removing the supporting-substrate so that the bottom surface of the semiconductor substrate is exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively, dicing the semiconductor substrate together with the supporting-substrate along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa
  • Publication number: 20190371893
    Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of silicon carbide, a device structure provided on top of the first semiconductor layer, a second semiconductor layer of silicon carbide having a higher impurity concentration than the first semiconductor layer, provided under the first semiconductor layer, the second semiconductor layer implementing an ohmic-contact, and a metallic electrode film provided under the second semiconductor layer. A thickness of a carbon-containing region in which carbon-atoms are precipitated between the second semiconductor layer and the metallic electrode film is 10 nm or less.
    Type: Application
    Filed: March 22, 2019
    Publication date: December 5, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi IGUCHI, Haruo NAKAZAWA, Yusuke WADA
  • Patent number: 10453687
    Abstract: A method of manufacturing a semiconductor device includes: forming, on a surface of an n-type semiconductor layer, an impurity source film containing both aluminum and beryllium; and forming a p-type impurity-doped layer in the n-type semiconductor layer by irradiating the impurity source film with first laser light to simultaneously introduce the aluminum and the beryllium into the n-type semiconductor layer.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa
  • Publication number: 20190228971
    Abstract: A doping system includes a light source to emit an optical pulse; a light source controller connected to the light source, to control an energy density of the optical pulse; and a beam adjusting unit to irradiate the optical pulse to a surface of a doping-object made of silicon carbide on which an impurity-containing source-film containing impurity atoms is deposited. The light source controller irradiates a first optical pulse to the impurity-containing source-film so as to form a reaction-product layer in the doping-object, and irradiates a second optical pulse having an energy density higher than an energy density of the first optical pulse, so as to introduce the impurity atoms into the target through the reaction-product layer.
    Type: Application
    Filed: November 27, 2018
    Publication date: July 25, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi IGUCHI, Haruo NAKAZAWA
  • Patent number: 10205010
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toru Muramatsu, Hong-fei Lu, Haruo Nakazawa
  • Publication number: 20190019679
    Abstract: A method of manufacturing a semiconductor device includes: forming, on a surface of an n-type semiconductor layer, an impurity source film containing both aluminum and beryllium; and forming a p-type impurity-doped layer in the n-type semiconductor layer by irradiating the impurity source film with first laser light to simultaneously introduce the aluminum and the beryllium into the n-type semiconductor layer.
    Type: Application
    Filed: June 6, 2018
    Publication date: January 17, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Kenichi IGUCHI, Haruo NAKAZAWA
  • Patent number: 10115587
    Abstract: A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 30, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Hidenao Kuribayashi, Hideaki Teranishi
  • Patent number: 10109501
    Abstract: A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 23, 2018
    Assignees: FUJI ELECTRIC CO., LTD., Octec, Inc.
    Inventors: Koh Yoshikawa, Haruo Nakazawa, Kenichi Iguchi, Yasukazu Seki, Katsuya Okumura
  • Publication number: 20180269314
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Toru MURAMATSU, Hong-fei LU, Haruo NAKAZAWA
  • Patent number: 10068998
    Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: September 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Michio Nemoto, Haruo Nakazawa
  • Patent number: 10026831
    Abstract: A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: July 17, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toru Muramatsu, Hong-fei Lu, Haruo Nakazawa
  • Patent number: 9972499
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a front surface and a back surface; forming a transition metal layer on a surface of the semiconductor substrate; and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves, to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of heat from the transition metal layer and, at an interface of the transition metal layer and the semiconductor substrate, an ohmic contact is formed by reaction of the transition metal layer and the semiconductor substrate, such as to form a transition metal silicide when the semiconductor substrate is silicon carbide. The ohmic contact provides a lower contact resistivity and device properties can be prevented from degrading.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 15, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi, Masaaki Tachioka, Kiyokazu Nakagawa
  • Patent number: 9905684
    Abstract: A semiconductor device includes a semiconductor substrate that is made of a semiconductor material with a wider band gap than silicon, a field effect transistor, including a front surface element structure, provided on a front surface of the substrate, and a drain electrode having surface contact with the substrate so as to form a Schottky junction between the semiconductor substrate and the drain electrode.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima