Patents by Inventor Haruo Nakazawa
Haruo Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8420512Abstract: A method for manufacturing a semiconductor device according to the invention irradiates a first pulse laser beam with an irradiation energy density of 1.0 J/cm2 or higher to blow off particles on the surface of wafer in activating an impurity layer positioned at a shallow location from the surface of wafer such as p+-type collector layer in an FS-type IGBT or in an NPT-type IGBT. By irradiating a second laser beam, region, on which particles were, is activated in the same manner as the region, on which particles are not, and p+-type collector layer is formed uniformly. The manufacturing method according to the invention facilitates preventing nonuniform laser beam irradiation from causing in laser annealing and preventing defective devices from causing.Type: GrantFiled: December 11, 2009Date of Patent: April 16, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Haruo Nakazawa
-
Publication number: 20120329257Abstract: A method for manufacturing a semiconductor device, the method including forming a front face structure of a semiconductor device on a first main face of a semiconductor substrate, grinding a second main face of the semiconductor substrate and reducing the semiconductor substrate in thickness to a thickness equal to or less than 100 ?m, ion implanting a dopant into the second main face of the semiconductor substrate of reduced thickness, and activating the dopant by irradiating the second main face with laser light and performing laser annealing while the semiconductor substrate of reduced thickness is heated.Type: ApplicationFiled: August 3, 2012Publication date: December 27, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventor: Haruo NAKAZAWA
-
Publication number: 20120184083Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.Type: ApplicationFiled: January 18, 2012Publication date: July 19, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
-
Publication number: 20120098085Abstract: A semiconductor device, and method of manufacturing the device, having a p type diffusion layer; a V-groove including a bottom surface parallel to the rear surface and exposing the p type diffusion layer and a tapered side surface rising from the bottom surface; a p type semiconductor layer on the rear surface surrounded by the tapered side surface of the V-groove; and a p type isolation layer formed on the side surface and electrically connecting the p type diffusion layer on the front surface and the p type semiconductor layer on the rear surface. The V-groove has a chamfered configuration around the intersection between a corner part of the side surface and the bottom surface of the V-groove. An object is to prevent performance degradation due to stress concentration at the corner part of a recessed part caused by thermal history in soldering.Type: ApplicationFiled: October 19, 2011Publication date: April 26, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Haruo NAKAZAWA, Takahito Harada, Fumio Shigeta, Kyohei Fukuda
-
Patent number: 8138542Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.Type: GrantFiled: April 21, 2009Date of Patent: March 20, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
-
Publication number: 20120064706Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.Type: ApplicationFiled: November 18, 2011Publication date: March 15, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Michio NEMOTO, Haruo NAKAZAWA
-
Patent number: 8119496Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: GrantFiled: May 24, 2010Date of Patent: February 21, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
-
Publication number: 20110318910Abstract: A method of manufacturing a semiconductor device that sufficiently activates a deep ion injection layer and fully recovers lattice defects generated in the ion injection process. Laser light pulses are successively emitted to form substantially CW (continuous wave) laser light. This feature of the invention stably performs activation of a deep ion injection layer at about 2 ?s with few defects.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: FUJI ELECTRIC CO., LTD.Inventors: Haruo NAKAZAWA, Motoyoshi Kubouchi
-
Patent number: 8084814Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.Type: GrantFiled: January 22, 2009Date of Patent: December 27, 2011Assignee: Fuji Electric Co., Ltd.Inventors: Michio Nemoto, Haruo Nakazawa
-
Publication number: 20110207267Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.Type: ApplicationFiled: February 10, 2011Publication date: August 25, 2011Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Haruo NAKAZAWA, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
-
Publication number: 20110081752Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: ApplicationFiled: May 24, 2010Publication date: April 7, 2011Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
-
Publication number: 20100264455Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: ApplicationFiled: June 28, 2010Publication date: October 21, 2010Applicant: FUJI ELECTRIC HOLDINGS CO. LTDInventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
-
Patent number: 7807554Abstract: A method of manufacturing a semiconductor element includes implanting ions of a dopant having a large diffusion coefficient into a semiconductor to provide a doped layer; and irradiating the doped layer with a plurality of pulsed laser beams supplied by a plurality of laser irradiation devices to activate the doped layer and provide an activated doped layer. The activated doped layer may be one of a single doped layer or a plurality of successive doped layers which each have respective conduction types that are one of identical or different. Device breakage and failure of the manufactured semiconductor element due to heat induced during laser irradiation are substantially prevented by this method.Type: GrantFiled: February 27, 2008Date of Patent: October 5, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventor: Haruo Nakazawa
-
Patent number: 7776672Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: GrantFiled: March 27, 2006Date of Patent: August 17, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
-
Publication number: 20100173476Abstract: A method for manufacturing a semiconductor device according to the invention irradiates a first pulse laser beam with an irradiation energy density of 1.0 J/cm2 or higher to blow off particles on the surface of wafer in activating an impurity layer positioned at a shallow location from the surface of wafer such as pt-type collector layer in an FS-type IGBT or in an NPT-type IGBT. By irradiating a second laser beam, region, on which particles were, is activated in the same manner as the region, on which particles are not, and pt-type collector layer is formed uniformly. The manufacturing method according to the invention facilitates preventing nonuniform laser beam irradiation from causing in laser annealing and preventing defective devices from causing.Type: ApplicationFiled: December 11, 2009Publication date: July 8, 2010Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventor: Haruo Nakazawa
-
Patent number: 7741192Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.Type: GrantFiled: August 19, 2005Date of Patent: June 22, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
-
Publication number: 20100093164Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.Type: ApplicationFiled: October 8, 2009Publication date: April 15, 2010Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
-
Publication number: 20090206398Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.Type: ApplicationFiled: April 21, 2009Publication date: August 20, 2009Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Koh YOSHIKAWA, Akio SUGI, Kouta TAKAHASHI, Manabu TAKEI, Haruo NAKAZAWA, Noriyuki IWAMURO
-
Publication number: 20090184340Abstract: A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 ?m to 30 ?m, both inclusively.Type: ApplicationFiled: January 22, 2009Publication date: July 23, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Michio NEMOTO, Haruo NAKAZAWA
-
Patent number: 7535059Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.Type: GrantFiled: November 28, 2006Date of Patent: May 19, 2009Assignee: Fuji Electric Holdings Co., Ltd.Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro