Abstract: A method for introducing impurity into a semiconductor substrate includes bringing a solution containing a compound of an impurity element into contact with a primary surface of a semiconductor substrate; and irradiating the primary surface of the semiconductor substrate with a laser beam through the solution to raise a temperature of the primary surface of the semiconductor substrate at a position irradiated by the laser beam so as to dope the impurity element into the semiconductor substrate. The laser beam irradiation is performed such that the raised temperature does not return to room temperature until a prescribed dose of the impurity element is caused to be doped into the semiconductor substrate.

Abstract: A first nickel film is deposited inside a contact hole of an interlayer dielectric formed on an n+-type SiC substrate. Irradiation with a first laser is carried out, forming an Ohmic contact with a silicon carbide semiconductor. A second nickel film and a front surface electrode film are deposited on the first nickel film, forming a source electrode. The back surface of the n+-type SiC substrate is ground, and a third nickel film is formed on the ground back surface of the n+-type SiC substrate. Irradiation with a second laser is carried out, forming an Ohmic contact with the silicon carbide semiconductor. A fourth nickel film and a back surface electrode film are deposited on the third nickel film, forming a drain electrode. By so doing, it is possible to prevent electrical characteristic deterioration of a semiconductor device, and to prevent warping and cracking of a wafer.

Abstract: A semiconductor device includes a semiconductor substrate that is made of a semiconductor material with a wider band gap than silicon, a field effect transistor, including a front surface element structure, provided on a front surface of the substrate, and a drain electrode having surface contact with the substrate so as to form a Schottky junction between the semiconductor substrate and the drain electrode.

Abstract: A semiconductor device includes an active region in which current flows when the semiconductor device is in an on state and a breakdown voltage structure portion which surrounds the active region. In the active region, a MOS gate structure includes, a p well region, an n+ source region, a gate electrode, and a source electrode is provided on the front surface of a semiconductor substrate. A drain electrode which comes into contact with an n? drift region is provided from the rear surface to the side surface of the semiconductor substrate. The drain electrode forms a Schottky contact with the n? drift region which is the semiconductor substrate. In the breakdown voltage structure portion, a leakage current reducing layer reduces leakage current from the outer circumferential edge of the semiconductor substrate and is provided at least at the outer circumferential edge of the semiconductor substrate.

Abstract: A semiconductor device and its method of manufacture. In the method, a front surface element structure is formed on a front surface of a semiconductor wafer, for example an SiC wafer. Then, a supporting substrate is bonded to wafer's front surface through an adhesive. The wafer's rear surface is ground and polished to thin it, with the supporting substrate bonded to the wafer. Next a V groove passing through the SiC wafer and reaching the adhesive is formed in the wafer's rear surface, and the wafer is cut into individual chips. An electrode film is formed on the groove's side wall and the chip's rear surface and a Schottky junction is formed between a drift layer, which is the chip, and the film. Then, the film is annealed. A tape is attached to the wafer's rear surface which has been cut into the chips. Then, the supporting substrate peels off from the wafer.

Abstract: In some aspects of the invention, a circuit pattern of a front surface structure is formed in a front surface of a semiconductor wafer and an alignment mark is formed on the front surface of a semiconductor wafer. A transparent supporting substrate is attached to the front surface of the semiconductor wafer by a transparent adhesive. Then, a resist is applied onto a rear surface of the semiconductor wafer. Then, the semiconductor wafer is mounted on a stage of an exposure apparatus, with the supporting substrate down. Then, the alignment mark formed on the front surface of the semiconductor wafer is recognized by a camera, and the positions of the semiconductor wafer and a photomask are aligned with each other. Then, the resist is patterned. Then, a circuit pattern is formed in the rear surface of the semiconductor wafer.

Abstract: A method for manufacturing a semiconductor device, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° C. and that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 ?m or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an oxygen atmosphere or a mixed gas atmosphere of oxygen and inert gas, and a second heat treatment performed in a nitrogen atmosphere or a mixed gas atmosphere of nitrogen and oxygen to form the diffusion layer. The method suppresses the occurrence of crystal defects, reduces the amount of inert gas used, and reduces manufacturing costs.

Abstract: A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate.

Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.

Abstract: In a method of manufacturing a reverse-blocking semiconductor element, a tapered groove is formed and ions are implanted into a rear surface and the tapered groove. Then, a furnace annealing process and a laser annealing process are performed to form a rear collector layer and a separation layer on the side surface of the tapered groove. In this way, it is possible to ensure a reverse breakdown voltage and reduce a leakage current when a reverse bias applied, even in a manufacturing method including a process of manufacturing a diffusion layer formed by forming a tapered groove and performing ion implantation and an annealing process for the side surface of the tapered groove as the separation layer for bending the termination of a reverse breakdown voltage pn junction to extend to the surface.

Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.

Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.

Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.

Abstract: A semiconductor device, and method of manufacturing the device, having a p type diffusion layer; a V-groove including a bottom surface parallel to the rear surface and exposing the p type diffusion layer and a tapered side surface rising from the bottom surface; a p type semiconductor layer on the rear surface surrounded by the tapered side surface of the V-groove; and a p type isolation layer formed on the side surface and electrically connecting the p type diffusion layer on the front surface and the p type semiconductor layer on the rear surface. The V-groove has a chamfered configuration around the intersection between a corner part of the side surface and the bottom surface of the V-groove. An object is to prevent performance degradation due to stress concentration at the corner part of a recessed part caused by thermal history in soldering.

Abstract: A semiconductor device includes an active region in which current flows when the semiconductor device is in an on state and a breakdown voltage structure portion which surrounds the active region. In the active region, a MOS gate structure includes, a p well region, an n+ source region, a gate electrode, and a source electrode is provided on the front surface of a semiconductor substrate. A drain electrode which comes into contact with an n? drift region is provided from the rear surface to the side surface of the semiconductor substrate. The drain electrode forms a Schottky contact with the n? drift region which is the semiconductor substrate. In the breakdown voltage structure portion, a leakage current reducing layer reduces leakage current from the outer circumferential edge of the semiconductor substrate and is provided at least at the outer circumferential edge of the semiconductor substrate.

Abstract: A semiconductor device and its method of manufacture. In the method, a front surface element structure is formed on a front surface of a semiconductor wafer, for example an SiC wafer. Then, a supporting substrate is bonded to wafer's front surface through an adhesive. The wafer's rear surface is ground and polished to thin it, with the supporting substrate bonded to the wafer. Next a V groove passing through the SiC wafer and reaching the adhesive is formed in the wafer's rear surface, and the wafer is cut into individual chips. An electrode film is formed on the groove's side wall and the chip's rear surface and a Schottky junction is formed between a drift layer, which is the chip, and the film. Then, the film is annealed. A tape is attached to the wafer's rear surface which has been cut into the chips. Then, the supporting substrate peels off from the wafer.

Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.

Abstract: In a method of manufacturing a reverse-blocking semiconductor element, a tapered groove is formed and ions are implanted into a rear surface and the tapered groove. Then, a furnace annealing process and a laser annealing process are performed to form a rear collector layer and a separation layer on the side surface of the tapered groove. In this way, it is possible to ensure a reverse breakdown voltage and reduce a leakage current when a reverse bias applied, even in a manufacturing method including a process of manufacturing a diffusion layer formed by forming a tapered groove and performing ion implantation and an annealing process for the side surface of the tapered groove as the separation layer for bending the termination of a reverse breakdown voltage pn junction to extend to the surface.

Abstract: A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element.

Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.