Patents by Inventor Haruo Nakazawa

Haruo Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7517777
    Abstract: The method of manufacturing a semiconductor device includes forming a p-type anode layer and an anode electrode on one major surface of an n-type semiconductor substrate, irradiating an electron beam to the semiconductor substrate to introduce crystal defects into the semiconductor substrate, grinding the other major surface of semiconductor substrate to reduce the thickness the semiconductor substrate, implanting phosphorus ions from the exposed surface of semiconductor substrate, and irradiating pulsed YAG laser beams by the double pulse technique to the exposed surface, from which the phosphorus ions have been implanted, to activate the implanted phosphorus atoms and to recover the region extending from the exposed surface irradiated with the YAG laser beams to the depth corresponding to 5 to 30% of the total wafer thickness from the defective state caused by the crystal defects introduced therein.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: April 14, 2009
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Michio Nemoto, Mitsuaki Kirisawa, Haruo Nakazawa
  • Publication number: 20080227277
    Abstract: A method of manufacturing a semiconductor element includes implanting ions of a dopant having a large diffusion coefficient into a semiconductor to provide a doped layer; and irradiating the doped layer with a plurality of pulsed laser beams supplied by a plurality of laser irradiation devices to activate the doped layer and provide an activated doped layer. The activated doped layer may be one of a single doped layer or a plurality of successive doped layers which each have respective conduction types that are one of identical or different. Device breakage and failure of the manufactured semiconductor element due to heat induced during laser irradiation are substantially prevented by this method.
    Type: Application
    Filed: February 27, 2008
    Publication date: September 18, 2008
    Applicant: Fuji Electric Device Technology Co., Ltd
    Inventor: Haruo Nakazawa
  • Publication number: 20070158740
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Application
    Filed: November 28, 2006
    Publication date: July 12, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
  • Publication number: 20070048982
    Abstract: The method of manufacturing a semiconductor device includes forming a p-type anode layer and an anode electrode on one major surface of an n-type semiconductor substrate, irradiating an electron beam to the semiconductor substrate to introduce crystal defects into the semiconductor substrate, grinding the other major surface of semiconductor substrate to reduce the thickness the semiconductor substrate, implanting phosphorus ions from the exposed surface of semiconductor substrate, and irradiating pulsed YAG laser beams by the double pulse technique to the exposed surface, from which the phosphorus ions have been implanted, to activate the implanted phosphorus atoms and to recover the region extending from the exposed surface irradiated with the YAG laser beams to the depth corresponding to 5 to 30% of the total wafer thickness from the defective state caused by the crystal defects introduced therein.
    Type: Application
    Filed: August 14, 2006
    Publication date: March 1, 2007
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Michio NEMOTO, Mitsuaki KIRISAWA, Haruo NAKAZAWA
  • Patent number: 7135387
    Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: November 14, 2006
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Haruo Nakazawa, Mitsuaki Kirisawa, Kazuo Shimoyama
  • Publication number: 20060249797
    Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.
    Type: Application
    Filed: March 27, 2006
    Publication date: November 9, 2006
    Applicant: FUJI ELECTRIC HOLDING CO., LTD.
    Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
  • Publication number: 20060038206
    Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.
    Type: Application
    Filed: August 19, 2005
    Publication date: February 23, 2006
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
  • Publication number: 20050059263
    Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.
    Type: Application
    Filed: June 24, 2004
    Publication date: March 17, 2005
    Inventors: Haruo Nakazawa, Mitsuaki Kirisawa, Kazuo Shimoyama