Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

Abstract: A simulation analysis system for dioxin concentration in furnace of municipal solid waste incineration process includes an area division module, the area division module is connected with a numerical simulation module, the numerical simulation module is connected with a single-factor analysis module, the single-factor analysis module includes an orthogonal test analysis module, and the orthogonal test analysis module is connected with a control module; the area division module is used for dividing areas in the incinerator, the numerical simulation module is used for conducting modeling simulation on the divided areas, the single-factor analysis module is used for conducting single-factor analysis according to the output of the numerical simulation module, and the orthogonal test analysis module is used for conducting orthogonal test analysis according to the output of the numerical simulation module.

Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The method includes receiving, from a base station (BS), a Radio Resource Control (RRC) configuration to configure a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and generating first uplink control information (UCI) in response to the first SPS PDSCH, where the RRC configuration includes a first parameter that indicates a priority of the first UCI.

Abstract: In some embodiments of the present disclosure, a sustained release osmotic-controlled pharmaceutical composition is provided, including: a core and a semi-permeable membrane coated on the core. The core includes a drug compartment, in which the drug compartment includes a first active ingredient, a first polymer and a first osmogen, and the first active ingredient includes lurasidone, a pharmaceutical acceptable salt of the lurasidone or a combination thereof. The semi-permeable membrane includes a membrane body and at least one pore distributed in the membrane body.

Abstract: A power decentralized electric locomotive apparatus includes an electric locomotive and a plurality of muck trucks. The electric locomotive and the plurality of muck trucks are connected in sequence, and a mater drive motor is fixedly mounted on the electric locomotive. A slave drive motor is fixedly mounted on at least one of the muck trucks; a torque of the slave drive motor is smaller than a torque of the mater drive motor; and the slave drive motor cooperates with the mater drive motor, to enable the muck truck to travel on rails and reduce drive power and self-weight of the electric locomotive.

Abstract: A method includes receiving a wafer, measuring a surface topography of the wafer; calculating a topographical variation based on the surface topography measurement performing a single-zone alignment compensation when the topographical variation is less than a predetermined value or performing a multi-zone alignment compensation when the topographical variation is greater than the predetermined value; and performing a wafer alignment according to the single-zone alignment compensation or the multi-zone alignment compensation.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: The present disclosure discloses a method for dual-motor control on an electric vehicle based on adaptive dynamic programming. First, total torque required is calculated based on obtained data information of the electric vehicle under various driving conditions, and offline training is conducted on an execution network and an evaluation network. Then total torque is dynamically distributed for two motors of the electric vehicle under various driving conditions to obtain an efficiency MAP database. Afterwards, iteration and online learning are conducted on the execution network and the evaluation network based on data information of the electric vehicle under different driving conditions that is obtained in real time, so as to find an optimal control law for the electric vehicle under a real-time driving condition. In this way, the dual-motor control on the electric vehicle is optimized.

Abstract: In embodiments a component includes a semiconductor layer sequence having a p-side semiconductor layer, an n-side semiconductor layer and an active zone located therebetween, wherein the active zone has a multiple quantum well structure including a plurality of quantum barrier layers and quantum well layers, the quantum barrier layers and the quantum well layers being arranged alternately along a vertical direction, wherein the active zone has at least one recess having facets extending obliquely to a main surface of the active zone, the recess being opened towards the p-side semiconductor layer, wherein, at least within the recess, the quantum barrier layers are n-doped and have a non-constant doping profile so that the component is configured to increase transport negatively charged charge carriers, from the n-side semiconductor layer towards the p-side semiconductor layer, based on the non-constant doping profile, and wherein, from the n-side semiconductor layer towards the p-side semiconductor layer, dopa

Abstract: A composition containing recombinant collagen with repairing and soothing effects, eye cream containing the composition and preparation method thereof are provided. The composition contains the following raw materials in parts by weight: 1 to 10 parts of recombinant collagen, 1 to 10 parts of sodium hyaluronate, 1 to 5 parts of bifida ferment lysate, 1 to 15 parts of glucosylglycerol, 1 to 10 parts of bisabolol, 1 to 15 parts eight-treasure essence stock solution, and 1 to 15 parts of pink red plum rechecking essence. The composition features with good skin permeability, contributing to its significant effects on repairing skin barriers and relieving skin inflammation, as well as its advantages of low irritation and high safety. Thus, the composition is suitable for people with damaged eye skin and has good market application prospects.

Abstract: A recombinant AAV vector including a sequence for introducing the expression of G protein-coupled receptor 173 (GPR173) and specifically targeting GPR173 expressing neurons in a brain is provided. A method of restoring the excitatory/inhibitory (E/I) balance in brain or for prophylaxis and/or therapy of a neurological condition in a subject in need thereof by administrating the recombinant AAV vector or a GPR173 agonist to the subject is also provided.

Abstract: In various embodiments, a training application trains a convolutional neural network to downsample images in a video encoding pipeline. The convolution neural network includes at least two residual blocks and is associated with a downsampling factor. The training application executes the convolutional neural network on a source image to generate a downsampled image. The training application then executes an upsampling algorithm on the downsampled image to generate a reconstructed image having the same resolution as the source image. The training application computes a reconstruction error based on the reconstructed image and the source image. The training application updates at least one parameter of the convolutional neural network based on the reconstruction error to generate a trained convolutional neural network.

Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

Abstract: Systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections. The power circuitry may include a string of diodes, connections to power lines, and particular diodes for voltage pull-up and pull-down clamping. There may be both a pull-up third diode in the diode string for connection between I/O and VDD and a pull-down third diode between I/O and VSS. During an ESD event the ESD device is configured to hold voltage from exceeding a threshold voltage and damaging internal circuitry. During operational mode the ESD device is turned off and does not interfere with circuit operations.