Abstract: In various embodiments, a training application trains a convolutional neural network to downsample images in a video encoding pipeline. The convolution neural network includes at least two residual blocks and is associated with a downsampling factor. The training application executes the convolutional neural network on a source image to generate a downsampled image. The training application then executes an upsampling algorithm on the downsampled image to generate a reconstructed image having the same resolution as the source image. The training application computes a reconstruction error based on the reconstructed image and the source image. The training application updates at least one parameter of the convolutional neural network based on the reconstruction error to generate a trained convolutional neural network.

Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

Abstract: The present invention provides a bispecific CS1-BCMA CAR-T cell and an application thereof. Specifically, the present invention provides a bispecific CAR, which comprises CS1 scFv and BCMA scFv, and a 4-1BB co-stimulatory domain and a CD3 activation domain. The bispecific CAR-T cell in the present invention has a significant killing effect on CS1 positive target cells and BCMA positive target cells, and can secrete IFN-? against target cells and significantly inhibit the growth of RPMI8226 xenograft tumor in an in vivo experiment. The present invention further provides a preparation method and an application of the bispecific CAR-T cell.

Abstract: Systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections. The power circuitry may include a string of diodes, connections to power lines, and particular diodes for voltage pull-up and pull-down clamping. There may be both a pull-up third diode in the diode string for connection between I/O and VDD and a pull-down third diode between I/O and VSS. During an ESD event the ESD device is configured to hold voltage from exceeding a threshold voltage and damaging internal circuitry. During operational mode the ESD device is turned off and does not interfere with circuit operations.

Abstract: A synchronous write method includes: receiving a synchronous write command of a process; if a process state table indicates that another synchronous write command of the process has not been added to a command queue, adding the synchronous write command to the command queue; if the process state table indicates that the other synchronous write command has been added to the command queue, adding an order preserving command to the command queue, and then adding the synchronous write command to the command queue; and sending commands in the command queue to a storage device according to the order of the commands in the command queue. The order preserving command is used to indicate that a synchronous write commands located before the order preserving command in the command queue is to be executed prior to the synchronous write command by the storage device.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A semiconductor device includes at least one fin, a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the at least one fin. The second dielectric layer between the at least one fin and the first dielectric layer. A thickness of the first dielectric layer on a sidewall of the at least one fin is less than a thickness of the second dielectric layer on the sidewall of the at least one fin.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A display device includes a first substrate, a plurality of light-emitting diodes, a first wavelength conversion layer and a metasurface. The light-emitting diodes are arranged on the first substrate, in which the light-emitting diodes emit a first color light, and the light-emitting diodes includes a first light-emitting diode, a second light-emitting diode and a third light-emitting diode. The first wavelength conversion layer is on the first light-emitting diode, and configured to convert the first color light emitted from the first light-emitting diode into a second color light, in which the second color light is different from the first color light. The metasurface is above the first wavelength conversion layer, and configured to reflect the first color light and pass the second color light.

Abstract: A method for producing a carotenoid or apocarotenoid is disclosed. The method comprises the step of expressing in a host cell an expression module comprising an expression vector having a coding region encoding at least one optimised carotenoid or apocarotenoid generating enzyme, the coding region being operably linked to a promoter. A host cell comprising an expression vector having a coding region encoding at least one optimised carotenoid or apocarotenoid generating enzyme, the coding region being operably linked to a promoter is also provided together with a kit.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: An epitaxial structure includes a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, and a buffer layer structure. The light emitting layer is disposed on the first type semiconductor layer. The second type semiconductor layer is disposed on the light emitting layer. The buffer layer structure is disposed on one side of the first type semiconductor layer away from the second type semiconductor layer and includes a first buffer layer and a second buffer layer. The second buffer layer is located between the first buffer layer and the first type semiconductor layer, and the first buffer layer has a chlorine concentration greater than a chlorine concentration of the second buffer layer.

Abstract: Disclosed are a reusable freely-shapable eco-friendly recycled brick manufacturing process and its product. The manufacturing process includes the steps of: (S1): preparing a raw material of a calcium silicate board; (S2): preparing a raw material of a gypsum board, mixing it with the raw material of the calcium silicate board obtained in (S1) and crushing them into fine powder; (S3): preparing a raw cement and mix it with the fine powder obtained in (S2); (S4): preparing raw water and mix it with the mixture obtained in (S3); (S5): preparing an enhancer and mix it with the mixture obtained in (S4), wherein the enhancer includes little surfactant and adhesive; (S): uniformly mix the raw materials prepared according to the eco-friendly recycled brick manufacturing process and their proportion, and pouring them into at least one mold; and (S7): forming the eco-friendly recycled brick product.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.