Patents by Inventor Heng Chen

Heng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11685985
    Abstract: A method of manufacturing a metal mask includes calendering a metal material, so as to form a metal mask substrate, where the metal mask substrate includes a surface and a plurality of grooves formed in the surface, and the grooves all extend in a direction. The surface has at least one sampling region, while at least two grooves are distributed in the sampling region, where an average area ratio of the area of the grooves within the sampling region to the area of the sampling region ranges between 45% and 68%.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: June 27, 2023
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Yun-Heng Chen, Wen-Yi Lin
  • Publication number: 20230186435
    Abstract: In various embodiments, an image preprocessing application preprocesses images. To preprocess an image, the image preprocessing application executes a trained machine learning model on first data corresponding to both the image and a first set of components of a luma-chroma color space to generate first preprocessed data. The image preprocessing application executes at least a different trained machine learning model or a non-machine learning algorithm on second data corresponding to both the image and a second set of components of the luma-chroma color space to generate second preprocessed data. Subsequently, the image preprocessing application aggregates at least the first preprocessed data and the second preprocessed data to generate a preprocessed image.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Christos G. BAMPIS, Li-Heng CHEN, Aditya MAVLANKAR, Anush MOORTHY
  • Patent number: 11670154
    Abstract: The present disclosure provides systems and methods for controlling a semiconductor manufacturing apparatus. A control system includes an inspection unit capturing a set of images of the semiconductor manufacturing apparatus, a sensor interface receiving the set of images and generating at least one input signal for a database server, and a control unit. The control unit includes a front end subsystem, a calculation subsystem, and a message and feedback subsystem. The calculation subsystem receives the data signal from the front end subsystem, wherein the calculation subsystem performs an artificial intelligence analytical process to determine, according to the data signal, whether a malfunction has occurred in the semiconductor manufacturing apparatus and to generate an output signal. The message and feedback subsystem generates an alert signal and a feedback signal according to the output signal, and the alert signal is transmitted to a user of the semiconductor manufacturing apparatus.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: June 6, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tso-Hsin Lin, Chung-Heng Chen, Jun-De Lee
  • Publication number: 20230170696
    Abstract: A control device for controlling a power generation system comprises a reception module, for receiving environmental data from the power generation system; an environment generation module, coupled to the reception module, for generating an environment state of the power generation system according to the environment data and an environment model; a strategy generation module, coupled to the environment generation module, for generating a power of the power generation system according to the environmental state, and for generating a control strategy of the power generation system according to the power; a transmission module, coupled to the strategy generation module, for transmitting the control strategy to the power generation system.
    Type: Application
    Filed: January 10, 2022
    Publication date: June 1, 2023
    Applicant: National Cheng Kung University
    Inventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Po-Hung Lin, Yi-Heng Chen, Ping-Han Huang
  • Publication number: 20230146059
    Abstract: An electronic device includes a substrate; a first electrode layer disposed on the substrate; a first insulating layer disposed on the first electrode layer, having a first opening to expose a surface of the first electrode layer; a connecting layer, wherein at least a portion of the connecting layer is disposed in the first opening, a sidewall exposure of the first opening is exposed, and the connecting layer is electrically connected to the first electrode layer; a second insulating layer disposed on the first insulating layer, having a second opening to expose a surface of the connecting layer; and a second electrode layer disposed on the second insulating layer, wherein at least a portion of the second electrode layer is disposed in the second opening, and is electrically connected to the connecting layer.
    Type: Application
    Filed: October 11, 2022
    Publication date: May 11, 2023
    Applicant: InnoLux Corporation
    Inventor: Yu-Heng CHEN
  • Publication number: 20230147849
    Abstract: Examples of computing devices for changing an operating mode thereof are described herein. In an example, a signal is received by the computing device from an electronic device having a contactless reader. The electronic device is connectable to the computing device. The computing device Is operated in one of a low-power operating mode and a full-power operating mode based on the received signal.
    Type: Application
    Filed: April 29, 2020
    Publication date: May 11, 2023
    Inventors: SHIH-HENG CHEN, HSIANG-TA KE, SHIH-HSIUNG TU, HENG-CHANG HSU
  • Patent number: 11646939
    Abstract: In a network function (NF) management method, a NF management device receives an NF discovery request sent by a first NF component, where the NF discovery request includes a second NF identifier that indicates a second NF. The NF management device obtains component information of a second NF component based on the second NF identifier, where the second NF component has the second NF, and the component information includes a discovery policy of the second NF component and a second NF component identifier. The NF management device determines, based on the discovery policy in the component information, that the first NF component can access the second NF component, and sends the second NF component identifier to the first NF component.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: May 9, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jingwang Ma, Heng Chen
  • Publication number: 20230133168
    Abstract: A method of detecting and identifying postures and gestures of a human user generates a reference model from a reference image and obtains an image of action or gesture being performed. The image is of a user and his flexible and hand-held portable device, and the image comprises a second identification feature. A state of a second feature of the second identification feature in the reference model can generate posture identification. The state of the second feature comprises size, shape, and location of the second identification feature in the hands of the user. A portable device and a non-volatile storage medium of a computer are also disclosed.
    Type: Application
    Filed: April 11, 2022
    Publication date: May 4, 2023
    Inventors: YU-HSIANG HAO, CHIEN-HENG CHEN, YAO-CHE PENG
  • Publication number: 20230138136
    Abstract: A method of forming a nanostructure field-effect transistor (nano-FET) device includes: forming a fin structure that includes a fin and alternating layers of a first semiconductor material and a second semiconductor material overlying the fin; forming a dummy gate structure over the fin structure; forming source/drain regions over the fin structure on opposing sides of the dummy gate structure; removing the dummy gate structure to expose the first and second semiconductor materials under the dummy gate structure; selectively removing the exposed first semiconductor material, where after the selectively removing, the exposed second semiconductor material remains to form nanostructures, where different surfaces of the nanostructures have different atomic densities of the second semiconductor material; forming a gate dielectric layer around the nanostructures, thicknesses of the gate dielectric layer on the different surfaces of the nanostructures being formed substantially the same; and forming a gate electrode
    Type: Application
    Filed: April 11, 2022
    Publication date: May 4, 2023
    Inventors: Yi-Shao Li, Shu-Han Chen, Chun-Heng Chen, Chi On Chui
  • Patent number: 11640977
    Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Ho Lin, Chun-Heng Chen, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20230125452
    Abstract: A semiconductor package includes a lead frame that includes a die pad and a plurality of leads, a semiconductor die mounted on a die attach surface of the die pad, an encapsulant body of electrically insulating material that covers semiconductor die and portions of the lead frame, and a fastener receptacle that includes a blind hole in the encapsulant body or the die pad, wherein a rear surface of the die pad is exposed from a first main face of the encapsulant body.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Inventors: Ryan Tordillo Comadre, Victor Dela Cruz Del Rosario, Bernie Tabanao Rosales, Subaramaniym Senivasan, Heng Chen Tang
  • Publication number: 20230126442
    Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.
    Type: Application
    Filed: May 9, 2022
    Publication date: April 27, 2023
    Inventors: Tsung-Ju Chen, Shu-Han Chen, Chun-Heng Chen, Chi On Chui
  • Publication number: 20230121800
    Abstract: An electrically-contactless joystick includes a housing, a handle, a first limiting member, a second limiting member, an elastic member, a magnet, and a magnetic sensor. The handle extends through the housing. The first limiting member and the second limiting member are fixed to the handle and movably clamped with the housing. The elastic member is connected to each of the first limiting member, the second limiting member, and the housing. The second limiting member abuts against the handle. The magnet is fixed to either the handle or the housing, and the magnetic sensor is fixed to the other. A terminal device is also provided.
    Type: Application
    Filed: September 23, 2022
    Publication date: April 20, 2023
    Inventors: YU-HSIANG HAO, CHIEN-HENG CHEN, CHENG-YEH SUN, YAO-CHE PENG
  • Publication number: 20230124471
    Abstract: A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Liao, Chih-Chung Chang, Chun-Heng Chen, Jiun-Ming Kuo
  • Publication number: 20230117889
    Abstract: A method for forming a semiconductor device structure includes forming alternating first semiconductor layers and second semiconductor layers stacked over a substrate. The method also includes etching the first semiconductor layers and the second semiconductor layers to form a fin structure. The method also includes oxidizing the first semiconductor layers to form first oxidized portions of the first semiconductor layers and oxidizing the second semiconductor layers to form second oxidized portions of the second semiconductor layers. The method also includes removing the oxides over the sidewalls of the second semiconductor layers. After removing the second oxidized portions, an upper layer of the second semiconductor layers is narrower than a lower layer of the second semiconductor layers. The method also includes removing the first semiconductor layers to form a gate opening between the second semiconductor layers. The method also includes forming a gate structure in the gate opening.
    Type: Application
    Filed: April 19, 2022
    Publication date: April 20, 2023
    Inventors: Yu-Ru Lin, Shu-Han Chen, Chun-Heng Chen, Chi On Chui
  • Patent number: 11606881
    Abstract: An electronic device is provided. The electronic device includes a housing, a first circuit board, and a first heat sink. The housing forms a receiving space. The first circuit board and the first heat sink are received in the receiving space along the gravity direction. One side of the first circuit board has at least one electronic element. The first heat sink has a first base board and at least first side board. The first base board is arranged adjacent to the first circuit board. The electronic element transferred heat to the first base board. The first side board connects to the first base board, and cooperatively forms a first heat dissipating channel along the gravity direction. The first side board is close to or contacts the housing, so that the heat of the electronic element can be transferred by heat conduction and heat convection to dissipate outside.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: March 14, 2023
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Chien Lee, Ying-Chih Liu, Pao-Heng Chen
  • Publication number: 20230068402
    Abstract: A controller assembly functioning as a joystick includes a driving unit, a sliding member, a potentiometer, and a controlling module. The driving unit includes a driving mechanism, a worm, and a worm wheel, the worm wheel connected to the sliding member. Through the worm, the driving mechanism rotates the worm wheel, causing the sliding member to move up and down only. The potentiometer detects rotation of the worm wheel, the controlling module obtains movement accordingly of the sliding member. The controlling module obtains a user's operating force applied to the driving mechanism, and compares the positional information and the operating force information with preset values to obtain comparison results. The sliding member is driven to move according to the two comparison results. An electronic device with the controller assembly is also disclosed.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 2, 2023
    Inventors: YU-HSIANG HAO, CHIEN-HENG CHEN, YAO-CHE PENG
  • Publication number: 20230037092
    Abstract: A method of manufacturing a metal mask includes calendering a metal material, so as to form a metal mask substrate, where the metal mask substrate includes a surface and a plurality of grooves formed in the surface, and the grooves all extend in a direction. The surface has at least one sampling region, while at least two grooves are distributed in the sampling region, where an average area ratio of the area of the grooves within the sampling region to the area of the sampling region ranges between 45% and 68%.
    Type: Application
    Filed: October 12, 2022
    Publication date: February 2, 2023
    Inventors: Yun-Heng CHEN, Wen-Yi LIN
  • Publication number: 20230036317
    Abstract: A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Kai-Heng CHEN, Pei-Haw TSAO, Shyue-Ter LEU, Rung-De WANG, Chien-Chun WANG
  • Publication number: 20230035349
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui