Patents by Inventor Hernan A. Castro

Hernan A. Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Path isolation in a memory device
    Patent number: 9978449
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventor: Hernan A. Castro
  • Memory tile access and selection patterns
    Patent number: 9959220
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 1, 2018
    Assignee: MICRON TECHNOLOGY, INC
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Accessing memory cells in parallel in a cross-point array
    Patent number: 9934850
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 3, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Hernan A. Castro
  • COMPENSATION FOR THRESHOLD VOLTAGE VARIATION OF MEMORY CELL COMPONENTS
    Publication number: 20180082728
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered.
    Type: Application
    Filed: August 29, 2017
    Publication date: March 22, 2018
    Inventors: Aswin Thiruvengadam, Hernan A. Castro
  • Methods and apparatuses for modulating threshold voltages of memory cells
    Patent number: 9905280
    Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY
    Publication number: 20170358353
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 14, 2017
    Inventor: Hernan Castro
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20170358348
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 14, 2017
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • APPARATUSES, DEVICES AND METHODS FOR SENSING A SNAPBACK EVENT IN A CIRCUIT
    Publication number: 20170358347
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Application
    Filed: July 31, 2017
    Publication date: December 14, 2017
    Inventors: Jeremy Miles Hirst, Hernan A. Castro, Stephen Tang
  • ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
    Publication number: 20170352410
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Application
    Filed: July 10, 2017
    Publication date: December 7, 2017
    Inventor: Hernan A. Castro
  • INTERCONNECTION FOR MEMORY ELECTRODES
    Publication number: 20170352387
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 7, 2017
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS
    Publication number: 20170352411
    Abstract: The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.
    Type: Application
    Filed: July 31, 2017
    Publication date: December 7, 2017
    Inventor: Hernan A. Castro
  • PATH ISOLATION IN A MEMORY DEVICE
    Publication number: 20170330621
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Application
    Filed: June 26, 2017
    Publication date: November 16, 2017
    Inventor: Hernan A. CASTRO
  • OPERATIONAL SIGNALS GENERATED FROM CAPACITIVE STORED CHARGE
    Publication number: 20170309333
    Abstract: Methods, a memory device, and a system. are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the memory cell to enter a conductive state. Once in the conductive state, the memory cell can be set or reset by a pulse formed from parasitic capacitive discharge from various paths coupled to the memory cell.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 26, 2017
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric S. Carman
  • Compensation for threshold voltage variation of memory cell components
    Patent number: 9786345
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 10, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aswin Thiruvengadam, Hernan A. Castro
  • Apparatuses and methods for efficient write in a cross-point array
    Patent number: 9779811
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 3, 2017
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventor: Hernan Castro
  • Interconnection for memory electrodes
    Patent number: 9767860
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 19, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Apparatuses, devices and methods for sensing a snapback event in a circuit
    Patent number: 9747981
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: August 29, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jeremy Hirst, Hernan Castro, Stephen Tang
  • Accessing memory cells in parallel in a cross-point array
    Patent number: 9741432
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 22, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Hernan A. Castro
  • Apparatuses and methods for bi-directional access of cross-point arrays
    Patent number: 9741433
    Abstract: The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 22, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Hernan A. Castro
  • Memory device architecture
    Patent number: 9734900
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst