Patents by Inventor Hernan A. Castro

Hernan A. Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • OPERATIONS ON MEMORY CELLS
    Publication number: 20190164611
    Abstract: In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventor: Hernan A. Castro
  • PULSED INTEGRATOR AND MEMORY TECHNIQUES
    Publication number: 20190156887
    Abstract: Methods, systems, and devices for a pulsed integrator and memory techniques are described. A first device may facilitate discharging a memory cell using at least one current pulse until a voltage associated with the memory cell reaches a reference voltage. The discharge time of the memory cell may be determined based at least in part on a duration of at least one current pulse. In some examples, a state of the memory cell may be determined based at least in part on a discharge time.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 23, 2019
    Inventors: Hernan A. Castro, Jeremy M. Hirst
  • RESET REFRESH TECHNIQUES FOR SELF-SELECTING MEMORY
    Publication number: 20190043580
    Abstract: Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 7, 2019
    Inventors: Agostino PIROVANO, Hernan A. CASTRO, Innocenzo TORTORELLI, Andrea REDAELLI
  • INTERCONNECTION FOR MEMORY ELECTRODES
    Publication number: 20190013052
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 10, 2019
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H.S. Tang
  • APPARATUSES, DEVICES AND METHODS FOR SENSING A SNAPBACK EVENT IN A CIRCUIT
    Publication number: 20190013067
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Application
    Filed: September 11, 2018
    Publication date: January 10, 2019
    Inventors: Jeremy Miles Hirst, Hernan A. Castro, Stephen Tang
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20190013068
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • MEMORY DEVICE ARCHITECTURE
    Publication number: 20190013069
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • COMPENSATION FOR THRESHOLD VOLTAGE VARIATION OF MEMORY CELL COMPONENTS
    Publication number: 20190006000
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 3, 2019
    Inventors: Aswin Thiruvengadam, Hernan A. Castro
  • APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY
    Publication number: 20180374537
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Inventor: Hernan Castro
  • CONNECTIONS FOR MEMORY ELECTRODE LINES
    Publication number: 20180374902
    Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
    Type: Application
    Filed: August 7, 2018
    Publication date: December 27, 2018
    Inventor: Hernan A. Castro
  • Compensation for threshold voltage variation of memory cell components
    Patent number: 10153019
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 11, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aswin Thiruvengadam, Hernan A. Castro
  • Memory device architecture
    Patent number: 10141051
    Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 27, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Jeremy M. Hirst
  • PATH ISOLATION IN A MEMORY DEVICE
    Publication number: 20180330789
    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 15, 2018
    Inventor: Hernan A. CASTRO
  • MEMORY TILE ACCESS AND SELECTION PATTERNS
    Publication number: 20180285287
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 4, 2018
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Apparatuses, devices and methods for sensing a snapback event in a circuit
    Patent number: 10083745
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 25, 2018
    Assignee: MICRON TECHNOLOGY, INC
    Inventors: Jeremy Miles Hirst, Hernan A. Castro, Stephen Tang
  • Apparatuses and methods for efficient write in a cross-point array
    Patent number: 10083752
    Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 25, 2018
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventor: Hernan Castro
  • Connections for memory electrode lines
    Patent number: 10074693
    Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: September 11, 2018
    Assignee: MICRON TECHNOLOGY, INC
    Inventor: Hernan A. Castro
  • Interconnection for memory electrodes
    Patent number: 10056120
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 21, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
    Publication number: 20180190349
    Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 5, 2018
    Inventor: Hernan A. Castro
  • APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS
    Publication number: 20180151206
    Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 31, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau