Abstract: Disclosed herein is a magnetic scale including a pipe, a strip-shaped magnetic member having a one side surface in the direction across the thickness thereof as a contact surface adapted to be closely attached to the inner surface of the pipe and the other side surface opposite to the one side surface as a back surface, the magnetic member being inserted in the pipe so as to extend straight in the longitudinal direction of the pipe, the magnetic member being formed with magnetic marks provided by a plurality of N poles and S poles alternately arranged in the longitudinal direction of the magnetic member, and a retainer member inserted in the pipe to press the back surface of the magnetic member toward the contact surface of the magnetic member, thereby maintaining a closely contact condition of the contact surface to the inner surface of the pipe. Accordingly, the magnetic member can be reliably protected to thereby improve its durability.

Abstract: The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Abstract: A magnetic scale is disclosed wherein a magnetic member is protected with certainty to effectively enhance the durability. The magnetic scale includes a magnetic member provided between outside and inside pipe members and has magnetic graduations magnetized alternately with the N and S poles along the extending direction thereof. When the magnetic member and the inside pipe member are assembled in the outside pipe member, the inside pipe member contacts partly with an inner face of the outside pipe member and partly with a back face of the magnetic member in such a manner as to cover the overall back face. The outer face of the inside pipe member presses the back face of the magnetic member over the overall length so that the close contact face of the magnetic member is closely contacted with the inner face of the outside pipe member.

Abstract: A magnetic scale includes a pipe and a polarizable magnetic member closely attached to the inner surface of the pipe so as to extend in the longitudinal direction of the pipe. The magnetic member is formed with magnetic marks provided by a plurality of N poles and S poles alternately arranged in the longitudinal direction of the magnetic member. Accordingly, the magnetic member can be reliably protected to thereby improve its durability.

Abstract: A circuit system, capable of further reducing power consumption without degrading performance, has been disclosed and comprises a plurality of circuit units, a power supply for supplying a plurality of power supplies of different voltages, a plurality of power supply selection circuits provided in accordance with each of the plurality of circuit units and selecting a power supply to be supplied to each circuit unit out of the plurality of power supplies of different voltages, and a control circuit for controlling the plurality of power supply selection circuits to select a power supply to be supplied to each circuit unit in accordance with the respective operation states of the plurality of circuit units, wherein each circuit unit uses a power supply selected by the power supply selection circuit as an internal power supply.

Abstract: A magnetic scale includes a pipe and a polarizable magnetic member closely attached to the inner surface of the pipe so as to extend in the longitudinal direction of the pipe. The magnetic member is formed with magnetic marks provided by a plurality of N poles and S poles alternately arranged in the longitudinal direction of the magnetic member. Accordingly, the magnetic member can be reliably protected to thereby improve its durability.

Abstract: A magnetic scale is disclosed wherein a magnetic member is protected with certainty to effectively enhance the durability. The magnetic scale includes a magnetic member provided between outside and inside pipe members and has magnetic graduations magnetized alternately with the N and S poles along the extending direction thereof. When the magnetic member and the inside pipe member are assembled in the outside pipe member, the inside pipe member contacts partly with an inner face of the outside pipe member and partly with a back face of the magnetic member in such a manner as to cover the overall back face. The outer face of the inside pipe member presses the back face of the magnetic member over the overall length so that the close contact face of the magnetic member is closely contacted with the inner face of the outside pipe member.

Abstract: Disclosed herein is a magnetic scale including a pipe, a strip-shaped magnetic member having a one side surface in the direction across the thickness thereof as a contact surface adapted to be closely attached to the inner surface of the pipe and the other side surface opposite to the one side surface as a back surface, the magnetic member being inserted in the pipe so as to extend straight in the longitudinal direction of the pipe, the magnetic member being formed with magnetic marks provided by a plurality of N poles and S poles alternately arranged in the longitudinal direction of the magnetic member, and a retainer member inserted in the pipe to press the back surface of the magnetic member toward the contact surface of the magnetic member, thereby maintaining a closely contact condition of the contact surface to the inner surface of the pipe. Accordingly, the magnetic member can be reliably protected to thereby improve its durability.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

Abstract: For the tradeoffs between a lower consumption power of a microprocessor and its process speed, a plurality of clocks and power supply voltages are supplied to each of functional units 104 to 107 and a clock switching circuit and a power switching circuit are provided in each of the functional units. When a program mainly using a particular functional unit, e.g., FPU 106, is executed, the operation speed of FPU 106 is raised more than that in a normal operation mode. To this end, a consumption power control circuit 102 supplies a power/clock switching signal 113c to FPU 106. This power/clock switching signal 113c instructs to raise the clock frequency and power supply voltage to be used by FPU 106. In order to compensate for an increase in the consumption power to be caused by the high speed operation of FPU 106, the consumption power control circuit 102 also supplies a power/clock signal 113b to another functional unit, e.g., CPU 105.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.

Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Abstract: In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: A data processing apparatus which processes data held in memory. The data processing apparatus includes an address operation unit which obtains an address to read one-word data from the memory, wherein the one-word data is a unit of data access to the memory, and a logical operation unit which determines a content of an operation on a field basis based on information which designates the number of bits per field to construct one-word data with a plurality of fields having a same number of bits. The logical operation unit, based on the content thus determined, performs the operation in parallel on the fields of the one-word data read from the memory by the address thus obtained.

Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.