Abstract: A method and apparatus for controlling a plurality of bus interfaces in a system including on one chip a central processing unit and an internal memory. A first operand retrieving operation is executed by a first operand retrieving unit when one operand is discriminated that is located outside a chip, and a second operand retrieving operation is executed by a second operand retrieving unit when another operand is discriminated that is located inside the chip, so that the operand is read to the central processing unit in accordance with the bus interface signals of the first and the second operand retrieving units.

Abstract: An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.

Abstract: An instruction is constituted by a plurality of words, minimum necessary information necessary for effective address calculation of an operand is stored in a leading word and a word or words containing an operation specification field (operation words) are arranged to continue the first word. According to this system, the operation word can be decoded concurrently with the address calculation of the operand or the operand fetch operation. Therefore, there is no need to secure a time exclusively for decoding the operation word and the execution speed of the instruction requiring the operand can be improved.

Abstract: A graphic pattern processing apparatus using a raster scan type CRT is disclosed. The graphic pattern processing apparatus can update one-pixel data, translate a logical address to a physical address and transfer data in a display memory, at a high speed. The graphic pattern processing apparatus comprises an operation unit including a logical address operation unit, a physical address operation unit, color data operation unit, and a control unit including a microprogram memory and a microprogram decoder.

Abstract: When a counter-part power supply designator of a first LSI designates that the counter-part power supply voltage of another LSI is a first power supply difference which is the same as the power supply difference of its own, an output circuit control controls an output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the first power supply voltage. When the counter-part power supply voltage designator designates that the counter-part power supply voltage difference, lower than the first power supply voltage difference, the output circuit control controls the output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the second power supply voltage difference. Thus, a plurality of LSIs can be operated at mutually different power supply voltages.

Abstract: A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.

Abstract: Micro instructions having a predetermined relationship with respect to each other are modified so that an original micro instruction and address assigned thereto can be restored by combining one or more modified micro instructions and address assigned thereto. A microprogram memory stores the micro instructions in such a modified form and at the modified address. When an original address is designated, one or more term lines are activated in a decoder of the microprogram memory, and modified micro instructions corresponding to the activated term lines are read-out from a memory array of the microprogram memory. The read modified micro instructions are logically combined to restore the original micro instruction. Thereby, the number of micro instructions to be actually stored in the microprogram memory can be reduced.

Abstract: A carry-look-ahead adder is provided which is implemented as a semiconductor integrated circuit. The integrated circuit includes a bipolar transistor coupled to the output terminal for providing an output indicative of the arithmetic operation. Impedance elements are coupled to the bipolar transistor and at least one FET is provided to control the on/off state of the bipolar transistor.

Abstract: Herein disclosed is a graphic processing apparatus which uses a CRT of raster scanning type. The graphic processing apparatus has functions to compare and judge whether or not within the range of a predetermined region thereby to effect the drawing operation, to compare drawing picture element data and other data in the drawing operation thereby to arithmetically control the drawing picture element data in accordance with the compared result, and to drawing a pattern of an arbitrary size on the basis of a fundamental unit of line and design patterns in the drawing operation.

Abstract: In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings.

Abstract: On a single semiconductor chip, there are provided an arithmetic logic unit, a general-purpose register for storing data to be processed and data as a result of the operation in the arithmetic logic unit, a peripheral register used for performing the peripheral functions required, a buffer register and an internal bus line through which the above mentioned components conduct the data communication with one another. Further, there is provided on the chip a microprogram storage and control device which stores microinstructions for processing instructions read out from a main memory (an instruction processing) and data processing necessary for performing the required peripheral functions (an auxiliary function processing).

Abstract: A semiconductor memory is provided including a plurality of row lines, memory cells driven by selecting a row line, sense amplifiers connected to the memory cells via column lines, and a column line voltage setting circuit for setting a predetermined voltage on the column lines. The predetermined voltage is defined by a voltage necessary to activate semiconductor switch elements constituting the column line voltage setting circuit, and is made nearly equal to the threshold voltage of the sense amplifiers. Thus, a high-speed, low power consumption semiconductor memory can be realized.

Abstract: The invention relates to a digital data processor based upon the pipeline control system, which is particularly effective when the time required for reading a microprogram is relatively short. A microcycle is based upon the time required for reading the microprogram, and the operations on the data is executed in a pipeline system by dividing it up according to the determined microcycle. This is done by providing a destination latch register on the output side of the arithmetic unit. The invention further deals with the processors in which the destination latch register is provided on the input side of the arithmetic unit, or when the destination latch register is incorporated within the arithmetic unit, and a circuit setup for avoiding any contention for a register that may develop when executing a current instruction and the next instruction is provided in accordance with an added microprogram.

Abstract: A semiconductor integrated circuit device provided with a flip-flop circuit including gates which are connected to each other so as to form a closed loop, is disclosed. The device includes: first means for generating a first write timing signal, a second write timing signal, a diagnosis control signal and diagnostic data which are all concerned with the flip-flop circuit, when the device is diagnosed to detect a fault therein; second means connected to the output side of the flip-flop circuit for making and breaking the closed loop of the gates in accordance with the first write timing signal; third means connected to the output side of the flip-flop circuit for supplying the diagnostic data to the flip-flop circuit in accordance with the second write timing signal; and fourth means connected to the input side of the flip-flop circuit for blocking a signal applied to the input side of the flip-flop circuit, in accordance with the diagnosis control signal.

Abstract: Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.

Abstract: A method of diagnosing an integrated circuit device having a plurality of combinational circuits, at least one input memory circuit connected to an input side of the combinational circuits, and an output memory circuit connected to an output side of the combinational circuits is disclosed. An input diagnostic signal is selectively applied to at least one input memory circuit connected to a given one of the combinational circuits, to read out a diagnostic signal stored in an output memory circuit connected to the given combinational circuit. Further, an integrated circuit device is disclosed which is suited to be diagnosed in the above method.

Abstract: An input/output control device stores variable-length data in a memory device at a high storage efficiency and without reducing the speed of data processing. The data stored in a memory are read out in the form of data of a fixed word length and then processed, the data having been processed are stored in another memory in the form of data of the fixed word length. The data stored in another memory are subjected to data organization to be outputted in the form of data of a given word length. Each of the memories is divided into a plurality of regions, and each region stores therein data of the same word length, respectively.

Abstract: A multi-computer system having a dual common memory adapted to perform Read/Write operations by means of a plurality of computers. Each computer in the system consists of a central processing unit, a main memory and a dual memory access unit. The dual memory access unit is adapted to provide a status signal representative of whether the data from the common memory is correct or not and a maintenance signal representative of whether a maintenance operation is demanded. A memory access is made only to the common memory demanding the maintenance when the program run by the computer is a maintenance program, and only to the normal common memory during the usual operation.

Abstract: A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

Abstract: A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.