Abstract: A microprogram control system in which the processing speed of a microprogram is increased and the capacity of the microprogram memory is reduced. The decoder previously provided in microprogram control systems to decode the contents of the instruction register are omitted to attain an increased processing speed and the instruction decoding function is integrated into the microprogram memory to attain a general purpose control system. The microprogram memory is divided into pages each consisting of a plurality of words, so that an arbitrary page can be designated as an instruction decode area under the control of the microprogram. Error checking in the system is facilitated by providing a check function for readout error, and a short word memory device is used to reduce the memory capacity of the microprogram memory.

Abstract: An LSI microprocessor comprising an instruction fetch portion and an instruction execute portion which fetches an instruction and executes an instruction independently of each other under a microprogram control, a pipeline control being made while synchronizing the portions, the instruction fetch portion containing therein an error processing circuit, which receives an external memory error signal concerning a main memory and an internal protect error signal and which delivers a reset signal for clearing a microprogram counter and starting an error processing microprogram.

Abstract: In an electronic computer system wherein, when a microprogram-controlled central processing unit receives a stop signal from a console, the contents of a group of registers are assigned to predetermined fixed areas in a main memory and, in response to a start signal, the assigned contents of the group of registers are delivered from the fixed areas to the group of registers. The reading and writing of the contents of the group of registers within the central processing unit is effected for the fixed areas of the main memory in which the contents are assigned.