Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1. and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

Abstract: A graphic pattern processing apparatus using a raster scan type CRT is disclosed. The graphic pattern processing apparatus can update one-pixel data, translate a logical address to physical address and transfer data in a display memory, at a high speed.

Abstract: The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Abstract: The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Abstract: In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunctional display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings.

Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Abstract: A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.

Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Abstract: A semiconductor integrated circuit memory device has at least two logic blocks, each logic block including at least two logic units and each logic unit having a number of metal oxide semiconductor field effect transistors (MOS FET's) integrated therein. Bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten a critical path of a logic block. The memory device may include a word driver circuit having a bipolar transistor connected to MOSFETs in an address decoder and memory cells of the memory device. The memory device may also include a sense circuit having a bipolar transistor for high speed discharge of a bit line, as well as an output buffer including a bipolar transistor for reducing signal transmission delays in driving a bus.

Abstract: In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings.

Abstract: A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single operation or an instruction having a long word length for indicating M (N<M) operations. When the number of operations to be executed in parallel is large, the long-word instruction is used. When it is small, the short-word instruction is used. A competition between the long-word instructions is detected by hardware and a competition between the short-word instructions only is detected by software. The simplification of the hardware brings about improvement of a machine cycle, improvement of a code cache hit ratio caused by the reduction of a code size and increase of the number of operations to be executed in parallel for the purpose of enhancing the performance.

Abstract: A graphic data generating apparatus includes a data processor, a graphic memory, and a graphic processor. The data processor outputs instructions to the graphic processor for processing graphic data. The instructions include a drawing instruction for transferring graphic data stored in a predetermined location in the graphic memory to another predetermined location in the graphic memory. The graphic memory stores pixel data defining the graphic data and each of the pixel data having a plurality of bits. The graphic processor performing read out of word data having a plurality of pixel data at a word position of the graphic memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the graphic memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Abstract: A graphic pattern processing apparatus having a display memory, a data processor, a graphic processor, and a plurality of parallel to serial convertors. The display memory stores graphic data in words, each word has a plurality of pixel data and each pixel data has a plurality of bits. A graphic processor accesses the display memory and processes a plurality of the pixel data in response to instructions received from a data processor. The number of parallel to serial convertors corresponds to the number of bits per pixel and are configured to allow a word from the display memory to be converted into a serial stream of pixel data.

Abstract: A graphic pattern processing apparatus for accessing a memory which stores words of graphic data. A plurality of pixels is stored in each word and each pixel has a plurality of bits. Each pixel of the word may be selected by a pixel address supplied by a graphic data processor. The graphic data processor performs processing on the selected pixel in accordance with instructions received from a data processor.

Abstract: A graphic pattern processing apparatus having a graphic memory, a data processor, and a graphic processor. The graphic memory stores a pattern composed of pixel data. The graphics processor includes a plurality of color registers. The graphic processor reads the graphic memory in response to instructions received from the data processor. The graphics processor in response to the pixel data read from the graphic memory selects one of a plurality of color registers and outputs that value.

Abstract: A data processing system having a logic LSI, a plurality of memory LSIs and a circuit which eliminates delays in the time at which data read out form the memory LSIs reach the logic LSI. The circuit includes variable delay circuits for delaying the data signals read out of the memory LSIs. A control circuit start monitors the time when the data read out of the individual memory LSIs arrive at flip-flops which output the data to the logic LSI. The delay times in the variable delay circuits are controlled by the control circuit for the individual memory LSIs so that the times the data read out from the memory LSIs reach the logic LSI may coincide with a predetermined standard time. Thus, the read data from the individual memory LSIs are caused to reach the flip-flops simultaneously.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.