Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device
A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
This application is a divisional application of U.S. application Ser. No. 10/493,443, filed Apr. 23, 2004, the contents of which are incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTIONThe present invention relates to a vertical MISFET, a semiconductor memory device, and their manufacturing methods and, particularly, to a technique effectively applied to a semiconductor memory device in which a transistor composed of a memory cell is constituted by a vertical MISFET (Metal Insulator Semiconductor Field Effect transistor).
BACKGROUND OF THE INVENTIONThe DRAM (Dynamic Random Access Memory) has been mainly used as a general-purpose and high-capacity semiconductor memory device. Memory cells in the DRAM are placed at the intersections between a plurality of word lines and a plurality of bit lines arranged in matrix on a main surface of a semiconductor substrate, and each is composed of one memory cell selecting MISFET and one capacitive element (capacitor) connected to this MISFET in series. The memory cell selecting MISFET is mainly composed of a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions constituting a source and a drain. The bit line is arranged on the memory cell selecting MISFET and electrically connected to one of the source and drain. Similarly, a data storage capacitor is arranged on the memory cell selecting MISFET and electrically connected to the other of the source and drain.
Japanese Patent Laid-Open No. 5-110019 discloses a one-transistor and one-capacitor semiconductor memory device in which a trench capacitor is formed in a semiconductor substrate and a vertical MIS transistor is arranged thereon.
Japanese Patent Laid-Open No. 11-87541 discloses another vertical MISFET, which is different from that shown in Japanese Patent Laid-Open No. 5-110019. In this vertical MISFET, a columnar laminated structure made of poly-crystalline silicon is provided on a semiconductor substrate, and a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) are formed in this order from below in the laminated structure. A sidewall of the intermediate semiconductor layer functions as a channel region and a gate insulating film is formed on the surface of the sidewall. Also, a gate electrode is formed on the sidewall of the laminated structure via the above-mentioned gate insulating film.
DISCLOSURE OF THE INVENTIONThe inventors of the present invention have been developing a semiconductor memory device using the vertical MISFET disclosed in Japanese Patent Laid-Open No. 11-87541. In this vertical MISFET, the source region, the channel forming region, and the drain region are formed in the columnar laminated structure formed on the semiconductor substrate. Therefore, there is an advantage of being capable of reducing an area occupied by the transistor. For example, if the trench capacitor is formed inside the trench formed in the semiconductor substrate and the memory cell selecting MISFET is formed thereon by using this vertical MISFET, it is possible to realize the memory cell with a smaller cell size than that of a conventional DRAM.
Meanwhile, since the source and drain regions of the vertical MISFET are formed by laminating poly-crystalline silicon films each having a high impurity concentration on and below the channel forming region composed of an undoped poly-crystalline silicon film or a poly-crystalline silicon film having a extremely low impurity concentration, the impurities in the source and drain are thermally diffused easily into the channel forming region by a thermal treatment during a process thereof.
However, since the leakage current (off current) during the time when the vertical MISFET is not operated is reduced by complete depletion of the channel forming region, there is the problem that if the impurities in the source and drain regions are thermally diffused in the channel forming region, the complete depletion of the channel forming region is hindered and the leakage current (off current) is increased. Additionally, the threshold voltage is varied due to the diffusion of the impurities into the channel forming region.
An object of the present invention is to provide a technique capable of achieving the vertical MISFET in which the leakage current (off current) is smaller.
An object of the present invention is to provide a technique capable of achieving the vertical MISFET in which the variation of the threshold voltage is reduced.
The above and other objects and novel characteristics of the present invention will be apparent from the description of the specification and the accompanying drawings.
Outlines of the typical ones of the inventions disclosed in this application will be briefly described as follows.
The present invention is a manufacturing method for a MISFET having a source region, a channel forming region, and a drain region formed over a main surface of a semiconductor substrate, and a gate electrode formed on a sidewall of said channel forming region via a gate insulating film, or is a manufacturing method for a semiconductor memory device provided with said MISFET, the method comprising the steps of: forming the source region containing a first impurity over the main surface of the semiconductor substrate; forming the channel forming region over said source region; introducing a second impurity of a conductivity type opposite to that of said first impurity into said channel forming region; and forming, over said channel forming region, the drain region containing said first impurity.
Also, the semiconductor memory device according to the present invention is provided with a MISFET having a source region, a channel forming region, and a drain region formed over a main surface of a semiconductor substrate, and a gate electrode formed on a sidewall of said channel forming region via a gate insulating film, wherein said source and drain regions are each composed of a poly-crystalline silicon film containing a first impurity, and said channel forming region is composed of a poly-crystalline silicon film containing a second impurity of a conductivity type opposite to that of said first impurity.
BRIEF DESCRIPTION OF THE DRAWINGS
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbol throughout the drawings for describing the embodiments and the repetitive description thereof will be omitted. Additionally, the description of the same or similar portion will not be repeated in principle except the case where the description is particularly required.
First EmbodimentIn this embodiment, the present invention is applied to a DRAM constituting a memory cell that is composed of one memory cell selecting MISFET and one capacitor, and a manufacturing method thereof will be described in order of process step with reference to FIGS. 1 to 24.
The memory cell is formed in the manner as follows. First, as shown in
Next, after removing the photoresist film 40 by ashing, trenches 4 each having a diameter of 120 nm and a depth of approximately 1 μm are formed in the memory cell forming region of the substrate 1 by the dry etching with using the silicon nitride film 3 as a mask, as shown in
Next, as shown in
Next, as shown in
The poly-crystalline silicon film 7 left in the trench 4 constitutes a storage electrode of the capacitor and also constitutes a source region of the memory cell selecting MISFET formed at the upper portion of the trench 4 in the subsequent step. Note that although the source region (poly-crystalline silicon film 7) can function as the drain region of the memory cell selecting MISFET, it is treated as the source region as a matter of convenience.
Through the process described above, the capacitor C having the n type semiconductor region 5 serving as a plate electrode, the silicon nitride film 6 serving as a capacitor insulating film, and the poly-crystalline silicon film 7 serving as a storage electrode is formed in the trench 4.
Next, as shown in
Next, a thermal treatment to the substrate 1 is performed to convert the above-mentioned amorphous silicon film 10a to a poly-crystalline silicon film 10 (
The above-mentioned poly-crystalline silicon film la may be formed of a poly-crystalline silicon film deposited by the CVD method. However, the film, obtained by performing the thermal treatment to and poly-crystallizing the amorphous silicon film 10a, becomes one better in film quality and fewer in crystal defect. Since the poly-crystalline silicon film 10 is used as the channel forming region of the memory cell selecting MISFET, it is desirable that the poly-crystalline silicon film 10 is formed by the methods capable of reducing as much crystal defects as possible.
When the above-mentioned thermal treatment is performed, a part of phosphorus contained in the n type poly-crystalline silicon film 7 (storage electrode and source region) formed below the poly-crystalline silicon film 10 is thermally diffused into the poly-crystalline silicon film 10 and the impurity concentration of the poly-crystalline silicon film 10 is increased. Therefore, it becomes difficult to achieve the complete depletion of the channel forming region formed of the poly-crystalline silicon film 10. Since the threshold voltage of the memory cell selecting MISFET is varied by phosphorus diffused into the channel forming region, there also arises the problem that the operation of the memory cell becomes unstable.
Consequently, boron (or BF2), which is of opposite conductivity type to that of phosphorus, is introduced into the poly-crystalline silicon film 10, as shown in
Thus, since boron of an opposite conductivity type and phosphorus diffused from the n type poly-crystalline silicon film (source region) 7 into the poly-crystalline silicon film (channel forming region) 10 are counter-doped in this embodiment, it is possible to reduce the effective impurity concentration in the poly-crystalline silicon film (channel forming region) 10.
Next, as shown in
Next, as shown in
Next, after removing the photoresist film 41 by the ashing, the poly-crystalline silicon film 12 and the poly-crystalline silicon film 10 are patterned by the dry etching with using the silicon nitride film 14 as a mask, as shown in
Next, as shown in
Next, as shown in
Next, after removing the photoresist film 42 by the ashing, the poly-crystalline silicon film 12 and the poly-crystalline silicon film 10 are patterned by the dry etching with using the strip-patterned silicon nitride film 16 as a mask, as shown in
After the above-mentioned dry etching, a quadratic-prism laminated structure P, in which the poly-crystalline silicon film 10, the poly-crystalline silicon film 12, the silicon oxide film 13, and the silicon nitride film 14 are laminated in this order, is formed on the capacitor C. Additionally, by forming this laminated structure P, a channel forming region 10C composed of the poly-crystalline silicon film 10 and a drain region 12D composed of the poly-crystalline silicon film 12 laminated thereon are formed. Two sidewalls (left and right sidewalls in
Next, as shown in
Next, as shown in
Through the process described so far, the memory cell of the DRAM composed of the capacitor C and the memory cell selecting MISFET Qs formed thereon is almost completed.
In the first embodiment, the ion implantation is performed twice, that is, the vertical ion implantation into the structure shown in
The vertical ion implantation shown in
Since the oblique ion implantation into the structure shown in
Although the reduction of the off current caused by the complete depletion and the reduction of the threshold voltage variation can be achieved by performing either of the two ion implantations, it is more preferable to perform both of the two ion implantations in view of the reproducibility and the controllability.
thus, in the first embodiment, since it is possible to reduce the effective impurity concentration in the channel forming region 10C of the memory cell selecting MISFET Qs, the channel forming region 10C can be completely depleted when the memory cell is not operated. Therefore, it is possible to manufacture the DRAM in which the off current (leakage current) is less. Additionally, since it is possible to control the variation of the threshold voltage of the memory cell selecting MISFET Qs, the reliability of the DRAM can be improved.
Second EmbodimentIn this embodiment, the present invention is applied to a p channel and vertical MISFET, and the manufacturing method thereof will be described in order of process with reference to FIGS. 25 to 35.
First, as shown in
Next, as shown in
Next, as shown in
By the above-mentioned thermal treatment for converting the amorphous silicon film 23a to the poly-crystalline silicon film 23, a part of boron contained in the p type poly-crystalline silicon film 21 formed under the poly-crystalline silicon film 23 passes through the thin silicon nitride film 22 and is thermally diffused in the poly-crystalline silicon film 23, and the impurity concentration in the poly-crystalline silicon film 23 is increased. Therefore, it becomes difficult to achieve the complete depletion of the channel forming region composed of the poly-crystalline silicon film 23. Additionally, the threshold voltage of the MISFET is varied due to the diffusion of phosphorus into the channel forming region, whereby there arises the problem that the operation of the memory cell becomes unstable.
So, an n type impurity of opposite conductivity type to that of boron (e.g., phosphorus, arsenic, or antimony) is introduced to the poly-crystalline silicon film 23, as shown in
Thus, in this embodiment, since boron diffused from the p type poly-crystalline silicon film 21 into the poly-crystalline silicon film 23 and the n type impurity of an opposite conductivity type are counter-doped, it is possible to reduce the effective impurity concentration in the poly-crystalline silicon film 23.
Next, as shown in
Next, after removing the photoresist film 43 by the ashing, as shown in
By the above-mentioned dry etching, a quadratic-prism laminate structure P, in which the poly-crystalline silicon film 21, the silicon nitride film 22, the poly-crystalline silicon film 23, the silicon nitride film 24, the poly-crystalline silicon film 25, and the silicon oxide film 26 are laminated in this order, is formed on the silicon oxide film 20. Additionally, by forming this laminated structure P, there are formed a source region 21S composed of the poly-crystalline silicon film 21 and a channel forming region 23C composed of the poly-crystalline silicon film 23 (and poly-crystalline silicon film 25) laminated thereon.
Next, as shown in
Next, as shown in
Next, the thermal treatment of the substrate 1 at a high temperature of approximately 900° C. to 1000° C. is performed to improve the film quality of the drain region 29D composed of the above-mentioned poly-crystalline silicon film. There is the problem that, when the above-mentioned thermal treatment is performed, a part of boron contained in the p type poly-crystalline silicon film constituting the drain region 29D is thermally diffused into the poly-crystalline silicon film 25 and the channel forming region 23C and the impurity concentration therein is increased. Additionally, there is also the problem that a part of boron contained in the source region 21S formed below the channel forming region 23C is thermally diffused into the channel forming region 23C.
For this reason, an n type impurity (phosphorus, arsenic, or antimony), which is of a conductivity type opposite to that boron, is introduced into the channel forming region 23C (poly-crystalline silicon films 23 and 25), as shown in
Thus, in this embodiment, since the boron diffused, into the channel forming region 23C, from the drain region 29D and the source region 21S each composed of a p type poly-crystalline silicon film, and the n type impurity (phosphorus, arsenic, or antimony) which is of an opposite conductivity type are counter-doped, it is possible to reduce the effective impurity concentration in the channel forming region 23C.
Next, as shown in
Next, as shown in
Through the process as described so far, there is completed the MISFET Qt composed of the source region 21S, the channel forming region 23C (poly-crystalline silicon films 23 and 25), the drain region 29D, the silicon oxide film 30 (gate insulating film), and the gate electrode 31G.
As described above, according to this embodiment, since it is possible to reduce the effective impurity concentration in the channel forming region 23C of the MISFET Qt, the channel forming region 23C can be completely depleted when the MISFET Qt is not operated. Therefore, it is possible to manufacture the MISFET in which the off current (leakage current) is less. Additionally, since it is possible to control the variation of the threshold voltage of the MISFET Qt, the operation reliability of the MISFET can be improved.
Third EmbodimentThe case where the n channel vertical MISFET is applied to the memory cell of the DRAM provided with a capacitor has been described in the first embodiment by way of an example. However, the present invention is not limited to the n channel vertical MISFET and the memory cell structure provided with the capacitor. More specifically, the present invention can be applied to the single vertical MISFET.
The source and drain of the n channel vertical MISFET are composed of polycrystalline silicon films each doped with phosphorus and formed by the CVD method. Since phosphorus from the source and drain is diffused in the poly-crystalline silicon film of the channel forming region, boron (or BF2) which is of a conductivity type opposite to that of phosphorus is introduced into the poly-crystalline silicon film of the channel forming region by the ion implantation method. This ion implantation is performed in the same manner as that described in the first embodiment. It is possible to reduce the effective impurity concentration in the channel by this ion implantation. Furthermore, the gate insulating film is formed by the thermal oxidation and the gate electrode is formed by the CVD method. By doing so, the n channel vertical MISFET is almost completed.
The source and drain of the p channel vertical MISFET is composed of a poly-crystalline silicon film doped with boron and formed by the CVD method. Since boron from the source and drain is diffused into the poly-crystalline silicon film of the channel forming region, phosphorus (arsenic or antimony) which is of a conductivity type opposite to that of boron is introduced by the ion implantation. This ion implantation can be achieved, by changing an ion seed from boron (or BF2) to an n type impurity (phosphorus, arsenic, or antimony) in the same manner as that of the ion implantation into the poly-crystalline silicon film of the channel forming region described in the first embodiment. It is possible to reduce the effective impurity concentration in the channel by this ion implantation. Furthermore, the gate insulating film is formed by the thermal oxidation and the gate electrode is formed by the CVD method. By doing so, the p channel vertical MISFET is almost completed.
As described above, according to this embodiment, since it is possible to reduce the effective impurity concentration in the channel forming region 23 of the MISFET Qt, the channel forming region 23C can be completely depleted when the MISFET Qt is not operated. Therefore, it is possible to manufacture the MISFET in which the off current (leakage current) is less. Additionally, since it is possible to control the variation of the threshold voltage of the MISFET Qt, the operation reliability of the MISFET can be improved.
In the foregoing, the invention made by the inventors has been concretely described based on the embodiments. However, needless to say, the present invention is not limited to the foregoing embodiments, and can be variously modified and altered without departing from the gist thereof.
The case where the present invention is applied to the manufacturing method of a DRAM has been described in the first embodiment. However, the present invention is not limited to this, and can be applied to various manufacturing methods of semiconductor memory devices each using, as a memory cell, the vertical MISFET disclosed in the present invention.
INDUSTRIAL APPLICABILITYSince it is possible to reduce the effective impurity concentration in the channel forming region of the MISFET, the channel forming region can be completely depleted when the MISFET is not operated. Therefore, it is possible to manufacture the memory cell in which the off current (leakage current) is less.
Also, since it is possible to reduce the variation of the threshold voltage of the MISFET, the MISFET with improved operation reliability can be manufactured.
Claims
1. A vertical MISFET manufacturing method, comprising the steps of:
- forming a lower semiconductor layer of a first conductivity type over a main surface of a semiconductor substrate;
- forming a diffusion barrier layer over said lower semiconductor layer;
- forming an intermediate semiconductor layer over said diffusion barrier layer;
- performing, after said step of forming the intermediate semiconductor layer, a thermal treatment to said semiconductor substrate; and
- patterning, after said step of performing the thermal treatment, at least said intermediate semiconductor layer and said lower semiconductor layer, thereby forming a columnar laminated structure,
- wherein said lower semiconductor layer constitutes one of a source and drain of said vertical MISFET, a gate electrode of said vertical MISFET is formed on a sidewall of said intermediate semiconductor layer via a gate insulating film, and
- an upper semiconductor layer constituting the other of the source and drain of said vertical MISFET is formed over said intermediate semiconductor layer.
2. The vertical MISFET manufacturing method according to claim 1,
- wherein a diffusion barrier layer is further formed between said upper semiconductor layer and said intermediate semiconductor layer.
Type: Application
Filed: Apr 24, 2007
Publication Date: Aug 30, 2007
Inventors: Tsuyoshi Tabata (Futaba), Kazuo Nakazato (Nagoya), Hiroshi Kujirai (Kunitachi), Masahiro Moniwa (Sayama), Hideyuki Matsuoka (Nishitokyo), Teruaki Kisu (Tokyo), Teruo Kisu (Tokyo), Haruko Kisu (Tokyo), Satoru Haga (Akishima)
Application Number: 11/790,130
International Classification: H01L 21/84 (20060101);