Patents by Inventor Hideyuki Nosaka
Hideyuki Nosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12206188Abstract: Arranged on a surface of a substrate are a patch conductor that radiates an electromagnetic field having been fed, a feed line that feeds the patch conductor with the electromagnetic field having been input, two slits parallel to the feed line on both sides of a connection part of the feed line toward an inner side of the patch conductor, and a ring conductor at a space from the patch conductor with an interposition of a gap to surround an outer periphery of the patch conductor. Accordingly, an electric capacitance can be formed between the patch conductor and the ring conductor, and when achieving impedance matching with the feed line, adjustment can be performed using the size of the ring conductor and the gap.Type: GrantFiled: October 31, 2019Date of Patent: January 21, 2025Assignee: Nippon Telegraph and Telephone CorporationInventors: Go Itami, Hiroshi Hamada, Hideyuki Nosaka
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Patent number: 12206373Abstract: A distributed amplifier includes: a transmission line having an input end that an input signal is input to; a transmission line having an output end that an output signal is output from; an input termination resistor connected to an end terminal of the transmission line; a plurality of unit cells arranged along the transmission lines, and having input terminals connected to the transmission line and output terminals connected to the transmission line; and a variable current source having one end connected to the end terminal of the transmission line and another end connected to a power supply voltage, and capable of adjusting a current amount between the transmission line and the power supply voltage.Type: GrantFiled: July 8, 2019Date of Patent: January 21, 2025Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 12176852Abstract: A voltage setting circuit includes a frequency comparator that compares the oscillation frequencies of a first distributed voltage-controlled oscillator and a second distributed voltage-controlled oscillator and a frequency determination circuit that determines the levels of the oscillation frequencies of the first distributed voltage-controlled oscillator and the second distributed voltage-controlled oscillator. The bias to be supplied to the first distributed voltage-controlled oscillator and the bias to be supplied to the second distributed voltage-controlled oscillator are determined in accordance with a result of the determination. The bias at a time when the levels of the oscillation frequencies are reversed is determined to be the optimum bias, and the optimum bias is supplied to the core circuit.Type: GrantFiled: February 18, 2021Date of Patent: December 24, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 12160205Abstract: An amplifier circuit comprises a variable degeneration circuit connected to emitter terminals of transistors, and a variable negative capacitance circuit connected to differential output signal terminals. The variable degeneration circuit includes a variable capacitor and a resistor. The variable negative capacitance circuit, which is a variable current source, includes a transistor, a capacitor, and a variable current source. The variable negative capacitance circuit includes transistors, a capacitor, and variable current sources.Type: GrantFiled: July 21, 2020Date of Patent: December 3, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 12119962Abstract: A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.Type: GrantFiled: August 5, 2019Date of Patent: October 15, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Naoki Terao, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 12101084Abstract: A driver circuit includes a differential pair of transistors that amplify differential input signals and output the amplified differential input signals from signal output terminals, a current source that supplies a constant current to the differential pair of transistors, a switch that stops the current supply from the current source to the differential pair of transistors during a shutdown mode period, capacitors each having one end connected to the ground, a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during an amplification mode period, and a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during the amplification mode period.Type: GrantFiled: December 12, 2019Date of Patent: September 24, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 12095182Abstract: Stub conductors are disposed so as to surround an outer periphery of a patch conductor and be spaced from the patch conductor with a gap positioned between the stub conductors and the patch conductor.Type: GrantFiled: April 20, 2020Date of Patent: September 17, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Go Itami, Hiroshi Hamada, Hideyuki Nosaka
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Patent number: 12095225Abstract: The DML driver includes: a post driver which supplies a driving current to the LD; and a pre-driver which drives the post driver in response to a modulated signal. The pre-driver has a transistor, a peaking inductor, a peaking inductor, a group delay inhibition inductor, and a peaking capacitor.Type: GrantFiled: March 12, 2020Date of Patent: September 17, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Toshiki Kishi, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 12050484Abstract: A clock generation circuit includes a mode-locked laser that generates an optical pulse, a photodiode that photoelectrically converts the optical pulse generated by the mode-locked laser, and a filter that attenuates at least one of a DC component and a harmonic component of the mode-locked laser included in an electric signal output from the photodiode.Type: GrantFiled: April 17, 2019Date of Patent: July 30, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Kenji Tanaka, Naoki Miura, Shinsuke Nakano, Hideyuki Nosaka
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Publication number: 20240235507Abstract: A distributed circuit includes: a first transmission line that has an input end to which an input signal is input; a second transmission line that has an output end from which an output signal is output; a plurality of unit cells that are disposed along the first and second transmission lines, the input terminals of the unit cells being connected to the first transmission line, the output terminals of the unit cells being connected to the second transmission line; two input termination resistors connected in parallel to an end of the first transmission line; and two output termination resistors connected in parallel to an end of the second transmission line. In the distributed circuit, at least one input termination resistor is a temperature-gradient resistor, and voltages at the two input termination resistors are changed symmetrically.Type: ApplicationFiled: February 22, 2021Publication date: July 11, 2024Inventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 12025642Abstract: A permittivity measuring method includes measuring a set of phases at sampling frequencies of at least three points in each of a first-half portion and a second-half portion of a phase characteristic of electromagnetic waves that passed through a measurement target, if the mode of the phase changes of both sets of phases belongs to a phase group in which change of the at least three points in the first half and change of at least three points in the second half are both monotonic change, maximal values, or minimal values, calculating the permittivity using the phase slope of the phases in the first-half portion and the phases in the second-half portion, and if the mode of the phase changes does not belong to the phase group, calculating the permittivity by fitting the phases of either the first half or the second half to a quadratic function.Type: GrantFiled: December 20, 2019Date of Patent: July 2, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Teruo Jo, Hiroshi Hamada, Hideyuki Nosaka
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Patent number: 12021494Abstract: An embodiment is a multiplexer including a first distributed amplifier with an impedance matched to 50?, the first distributed amplifier configured to receive a first signal and output a first amplified signal, a second distributed amplifier with an impedance matched to 50?, the second distributed amplifier configured to receive a second signal and output a second amplified signal, and a passive multiplexer configured to multiplex the first amplified signal and the second amplified signal, and output a multiplexed signal to a signal output terminal, the passive multiplexer including a first resistor having a first end to receive the first amplified signal, a second resistor having a first end to receive the second amplified signal, and a third resistor having a first end connected to second ends of the first and second resistors and a second end connected to the signal output terminal.Type: GrantFiled: June 26, 2020Date of Patent: June 25, 2024Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Publication number: 20240136990Abstract: A distributed circuit includes: a first transmission line that has an input end to which an input signal is input; a second transmission line that has an output end from which an output signal is output; a plurality of unit cells that are disposed along the first and second transmission lines, the input terminals of the unit cells being connected to the first transmission line, the output terminals of the unit cells being connected to the second transmission line; two input termination resistors connected in parallel to an end of the first transmission line; and two output termination resistors connected in parallel to an end of the second transmission line. In the distributed circuit, at least one input termination resistor is a temperature-gradient resistor, and voltages at the two input termination resistors are changed symmetrically.Type: ApplicationFiled: February 22, 2021Publication date: April 25, 2024Inventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Publication number: 20240130046Abstract: A capacitor includes a pair of facing stacked electrodes connected to an electrical wiring from the outside. The stacked electrode includes a plurality of wiring layers and a via layer between the wiring layers. The stacked electrode includes combs and a comb connection portion connected to base ends of the combs. A dielectric is provided between one stacked electrode and the other stacked electrode. The comb of the other stacked electrode is disposed between the combs of the one stacked electrode.Type: ApplicationFiled: February 22, 2021Publication date: April 18, 2024Inventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Publication number: 20240120883Abstract: A voltage-controlled oscillator includes a first unit cell, a second unit cell that is connected in parallel to the first unit cell via transmission lines, a compensation unit cell that is connected in parallel with the first unit cell and the second unit cell between the first unit cell and the second unit cell, and an input termination resistor that is connected to a power supply voltage terminal of each of the first unit cell, the second unit cell, and the compensation unit cell. Symmetrical voltages are supplied to the first unit cell and the second unit cell, and the compensation unit cell compensates for a gain by the first unit cell or the second unit cell.Type: ApplicationFiled: February 18, 2021Publication date: April 11, 2024Inventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 11942913Abstract: A gain adjustment unit constituted by a distribution switch having a control terminal is provided in an input unit of an amplifier circuit. One end of a coupler is connected to an output line of the amplifier circuit, another end of the coupler is connected to an anode of a diode, and a monitor terminal is connected via a low-pass filter to a cathode of the diode. The anode of the diode is unbiased.Type: GrantFiled: February 27, 2019Date of Patent: March 26, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Hiroshi Hamada, Hideyuki Nosaka
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Publication number: 20240080006Abstract: An embodiment differential amplifier circuit includes an amplifier section including differential pair transistors to which a differential signal is input and a tail current circuit made up of a short stub provided between a ground terminal of the amplifier section and a ground. In an embodiment, an electrical length of the short stub is shorter than a quarter wavelength of an operation frequency of the differential amplifier circuit.Type: ApplicationFiled: February 12, 2021Publication date: March 7, 2024Inventors: Hiroshi Hamada, Hideyuki Nosaka
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Publication number: 20240072733Abstract: A unit amplifier has first and second transistors, which are cascode-connected, and a first variable resistance circuit. A base terminal or a gate terminal of the first transistor is connected to a cell input terminal, a collector terminal or a drain terminal of the second transistor is connected to a cell output terminal, an emitter terminal or a source terminal of the second transistor is connected to a collector terminal or a drain terminal of the first transistor, and one end of the first variable resistance circuit is connected to a connecting point of the first and second transistors.Type: ApplicationFiled: December 17, 2020Publication date: February 29, 2024Inventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Publication number: 20240056029Abstract: A voltage setting circuit includes a frequency comparator that compares the oscillation frequencies of a first distributed voltage-controlled oscillator and a second distributed voltage-controlled oscillator and a frequency determination circuit that determines the levels of the oscillation frequencies of the first distributed voltage-controlled oscillator and the second distributed voltage-controlled oscillator. The bias to be supplied to the first distributed voltage-controlled oscillator and the bias to be supplied to the second distributed voltage-controlled oscillator are determined in accordance with a result of the determination. The bias at a time when the levels of the oscillation frequencies are reversed is determined to be the optimum bias, and the optimum bias is supplied to the core circuit.Type: ApplicationFiled: February 18, 2021Publication date: February 15, 2024Inventors: Teruo Jo, Munehiko Nagatani, Hideyuki Nosaka
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Patent number: 11888495Abstract: An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).Type: GrantFiled: October 23, 2019Date of Patent: January 30, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Munehiko Nagatani, Teruo Jo, Hiroshi Yamazaki, Hideyuki Nosaka