Abstract: A high-frequency module includes: a chassis which is made of a conductor and which has an internal space; a high-frequency circuit board which is housed in the internal space of the chassis; and a resistive element provided between an inner wall that opposes the high-frequency circuit board among inner walls of the chassis which define the internal space and the high-frequency circuit board.

Abstract: A distributed mixer is configured of an artificial transmission line of which an input end is connected to an LO terminal and a terminal end is connected to an IF terminal, an artificial transmission line of which an input end is connected to an RF terminal, FETs that perform frequency synthesis of LO signals and RF signals and that are disposed following the artificial transmission lines and of which gates are connected to the artificial transmission line and sources are grounded, a bias circuit that applies gate bias voltage to a terminal end of the artificial transmission line, a terminating resistor that connects the terminal end of the artificial transmission line and a ground, and a plurality of transmission lines provided between the artificial transmission line and a drain of each FET.

Abstract: A positive-side power supply terminal (1-1a) of a differential amplifier (1-1) is connected to a positive-side power supply line (L1). A negative-side power supply terminal (1-2b) of a differential amplifier (1-2) is connected to a negative-side power supply line (L2). A negative-side power supply terminal (1-1b) of the differential amplifier (1-1) and a positive-side power supply terminal (1-2a) of the differential amplifier (1-2) are connected to each other. A final-stage amplifier (2) is connected between the positive-side power supply line (L1) and the negative-side power supply line (L2).

Abstract: A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.

Abstract: A connection structure (3) of a high-frequency transmission line according to this invention includes a columnar central conductor (7) having one end connected to a coaxial line and the other end connected to a planar transmission line, a first outer conductor (41) arranged on a side of the one end of the central conductor coaxially with the central conductor, a first dielectric body (42) filled between the first outer conductor and the central conductor, a second outer conductor (61) arranged on a side of the other end of the central conductor coaxially with the central conductor, a second dielectric body (62) filled between the second outer conductor and the central conductor, a third outer conductor (51) arranged between the first outer conductor and the second outer conductor coaxially with the central conductor, and a third dielectric body (52) filled between the third outer conductor and the central conductor.

Abstract: An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE?the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

Abstract: A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.

Abstract: An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.

Abstract: A positive-side power supply terminal (1-1a) of a differential amplifier (1-1) is connected to a positive-side power supply line (L1). A negative-side power supply terminal (1-2b) of a differential amplifier (1-2) is connected to a negative-side power supply line (L2). A negative-side power supply terminal (1-1b) of the differential amplifier (1-1) and a positive-side power supply terminal (1-2a) of the differential amplifier (1-2) are connected to each other. A final-stage amplifier (2) is connected between the positive-side power supply line (L1) and the negative-side power supply line (L2).

Abstract: A connection structure (3) of a high-frequency transmission line according to this invention includes a columnar central conductor (7) having one end connected to a coaxial line and the other end connected to a planar transmission line, a first outer conductor (41) arranged on a side of the one end of the central conductor coaxially with the central conductor, a first dielectric body (42) filled between the first outer conductor and the central conductor, a second outer conductor (61) arranged on a side of the other end of the central conductor coaxially with the central conductor, a second dielectric body (62) filled between the second outer conductor and the central conductor, a third outer conductor (51) arranged between the first outer conductor and the second outer conductor coaxially with the central conductor, and a third dielectric body (52) filled between the third outer conductor and the central conductor.

Abstract: In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer.

Abstract: In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer.

Abstract: An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE?the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

Abstract: In the conventional technique, only an output having a bandwidth identical to the bandwidth of individual DACs has been obtained even by using a plurality of DACs. Also, even when the output of a bandwidth broader than the individual DAC is obtained, there has been a problem associated with asymmetricity of a circuit configuration. In a signal generating device of the present invention, a plurality of normal DACs are combined to realize an analog output of a broader bandwidth beyond the output bandwidth of the individual DACs, and the problem of the asymmetricity of the circuit configuration is also resolved. A desired signal is separated into a low-frequency signal and a high-frequency signal in a frequency domain, and a series of operation of constant (r)-folding the amplitude of the high-frequency signal and shifting it on the frequency axis to superimpose it on the low-frequency signal are made in a digital domain. The output of each DAC is switched by an analog multiplexer.

Abstract: An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.

Abstract: A frequency domain multiplexed signal receiving method which decodes received signals that are multiplexed in a frequency domain, includes: a digital signal acquisition step of acquiring digital signals from the received signals that are multiplexed in the frequency domain; an offset discrete Fourier transform step of applying an offset discrete Fourier transform to odd discrete point numbers based on the acquired digital signals; and a decode step of decoding frequency domain digital signals in the frequency domain obtained by the offset discrete Fourier transform, and that are the frequency domain digital signals of one or more frequency channels.

Abstract: An automatic gain control circuit (5a) includes a peak detector circuit (10) that detects the peak voltage of the output signal from a variable gain amplifier (3), an average value detection and output amplitude setting circuit (11) that detects the average voltage of the output signals from the variable gain amplifier (3) and adds a voltage ½ the desired output amplitude of the variable gain amplifier (3) to the average voltage, and a high gain amplifier (12) that amplifies the difference between the output voltage of the peak detector circuit (10) and the output voltage of the average value detection and output amplitude setting circuit (11) and controls the gain of the variable gain amplifier (3) using the amplification result as a gain control signal. The peak detector circuit (10) includes transistors (Q1, Q2, Q3), a current source (I1), and a filter circuit. The filter circuit includes a series connection of a resistor (Ra) and a capacitor (C1).

Abstract: An automatic gain control circuit (5a) includes a peak detector circuit (10) that detects the peak voltage of the output signal from a variable gain amplifier (3), an average value detection and output amplitude setting circuit (11) that detects the average voltage of the output signals from the variable gain amplifier (3) and adds a voltage ½ the desired output amplitude of the variable gain amplifier (3) to the average voltage, and a high gain amplifier (12) that amplifies the difference between the output voltage of the peak detector circuit (10) and the output voltage of the average value detection and output amplitude setting circuit (11) and controls the gain of the variable gain amplifier (3) using the amplification result as a gain control signal. The peak detector circuit (10) includes transistors (Q1, Q2, Q3), a current source (I1), and a filter circuit. The filter circuit includes a series connection of a resistor (Ra) and a capacitor (C1).

Abstract: A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.

Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.