Abstract: A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal.

Abstract: A digital signal process unit includes a first cancel signal generation unit and a second cancel signal generation unit. The first cancel signal generation unit generates, as a first cancel signal component, a cancel signal component corresponding to an image signal included in an analog signal output from a mixer. The second cancel signal generation unit generates, as a second cancel signal component, a cancel signal component corresponding to a leakage signal generated between an input and output of the mixer. The digital signal process unit includes subtractors for subtracting the first cancel signal component and the second cancel signal component from a signal component corresponding to a frequency band divided from an input signal to obtain a digital signal.

Abstract: A reception-side IC chip (1a) includes a pad (15) which is connected to a transmission line (2) which is outside the chip and has a characteristic impedance Z0 of 50 ?, a signal line (16), one end of which is connected to the pad (15), a reception-side input unit circuit (10) configured to receive a signal (S) transmitted from a transmission-side IC chip via the transmission line (2), a 50-? termination resistor (11), for impedance matching, which is connected between a predetermined voltage and the other end of the signal line (16) and is configured to terminate the transmission line (2), and a capacitor (12) inserted between a node (A) of the signal line (16) and the termination resistor (11) and an input terminal (In) of the reception-side input unit circuit (10). A DC-blocking circuit is formed by the capacitor (12).

Abstract: A negative capacitance circuit is connected between a drain and a source of the mixer transistor. With this configuration, the negative capacitance circuit is connected in parallel to a parasitic capacitance generated between the drain and the source of the mixer transistor, and the parasitic capacitance can be canceled out in a wide band by the negative capacitance circuit connected in parallel.

Abstract: A digital-to-analog converter includes a core circuit including a plurality of input terminals for multi-bit digital signals, an output terminal for an analog signal, a plurality of constant current sources, a plurality of switch circuits connected in series to respective constant current sources of the plurality of constant current sources, and a load resistor connected to the output terminal. The core circuit being configured to select whether or not to allow a current to flow through each of the plurality of switch circuits based on the multi-bit digital signals and output a voltage generated by allowing the current flowing through each of the plurality of switch circuits to flow through the load resistor from the output terminal as an analog signal.

Abstract: A source injection mixer includes an FET, an IF matching circuit between an IF port and a gate of the FET, and that matches impedance of the IF port and impedance of the gate as viewed from the IF port, a shorting stub of which one end is connected to a source of the FET and another end is grounded, and shorter than ¼ of an electric length at a frequency of LO signals, an LO matching circuit between an LO port and the source of the FET, and that matches impedance of the LO port and impedance of the source as viewed from the LO port, and an RF matching circuit between an RF port and a drain of the FET, and that matches impedance of the RF port and impedance of the drain as viewed from the RF port.

Abstract: A CMOS inverter circuit is provided as a circuit to modulate a current flowing into a laser diode on the basis of a digital signal. An amplitude of a current flowing in a PMOSFET in the CMOS inverter circuit is made to contribute to an amplitude of the current flowing into the laser diode, to reduce an input amplitude.

Abstract: Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit 1 including a differential amplifier circuit 10, a switch circuit 20, and a hold capacitor C21, the differential amplifier circuit 10 includes a first resistor R11 having one end connected to a collector electrode of a first transistor Q11 constituting a differential pair, a second resistor R12 having one end connected to the collector electrode of a second transistor Q12 constituting the differential pair, and a third resistor R13 to which the other end of the first resistor R11 and the other end of the second resistor R12 are connected and which is connected between the other ends and a power supply VCC.

Abstract: A gain adjustment unit constituted by a distribution switch having a control terminal is provided in an input unit of an amplifier circuit. One end of a coupler is connected to an output line of the amplifier circuit, another end of the coupler is connected to an anode of a diode, and a monitor terminal is connected via a low-pass filter to a cathode of the diode. The anode of the diode is unbiased.

Abstract: A high frequency connection structure includes: a waveguide; a ridge coupler constituted by a conductor formed inside one end of the waveguide; a transmission line adjacent to the one end of the waveguide; an inductance adjustment structure which is provided between the ridge coupler and the transmission line and which adjusts ground inductance that is created due to a connection between the ridge coupler and the waveguide; and a wire which connects one end of the ridge coupler on a side of the transmission line and one end of the transmission line with each other.

Abstract: A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal.

Abstract: A resistive mixer includes a LO matching circuit inserted between the gate of an FET and a LO terminal, a bias circuit that is connected to the gate and applies a bias voltage to the gate, an RF matching circuit inserted between the drain of the FET and an RF terminal, and an IF matching circuit inserted between the drain and an IF terminal. The source of the FET is grounded. The impedance of the RF matching circuit seen from the drain of the FET at an IF frequency is open-circuit, and the impedance of the IF matching circuit seen from the drain of the FET at an RF frequency is open-circuit.

Abstract: A high-frequency module includes: a chassis which is made of a conductor and which has an internal space; a high-frequency circuit board which is housed in the internal space of the chassis; and a resistive element provided between an inner wall that opposes the high-frequency circuit board among inner walls of the chassis which define the internal space and the high-frequency circuit board.

Abstract: A distributed mixer is configured of an artificial transmission line of which an input end is connected to an LO terminal and a terminal end is connected to an IF terminal, an artificial transmission line of which an input end is connected to an RF terminal, FETs that perform frequency synthesis of LO signals and RF signals and that are disposed following the artificial transmission lines and of which gates are connected to the artificial transmission line and sources are grounded, a bias circuit that applies gate bias voltage to a terminal end of the artificial transmission line, a terminating resistor that connects the terminal end of the artificial transmission line and a ground, and a plurality of transmission lines provided between the artificial transmission line and a drain of each FET.

Abstract: A positive-side power supply terminal (1-1a) of a differential amplifier (1-1) is connected to a positive-side power supply line (L1). A negative-side power supply terminal (1-2b) of a differential amplifier (1-2) is connected to a negative-side power supply line (L2). A negative-side power supply terminal (1-1b) of the differential amplifier (1-1) and a positive-side power supply terminal (1-2a) of the differential amplifier (1-2) are connected to each other. A final-stage amplifier (2) is connected between the positive-side power supply line (L1) and the negative-side power supply line (L2).

Abstract: A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.

Abstract: A connection structure (3) of a high-frequency transmission line according to this invention includes a columnar central conductor (7) having one end connected to a coaxial line and the other end connected to a planar transmission line, a first outer conductor (41) arranged on a side of the one end of the central conductor coaxially with the central conductor, a first dielectric body (42) filled between the first outer conductor and the central conductor, a second outer conductor (61) arranged on a side of the other end of the central conductor coaxially with the central conductor, a second dielectric body (62) filled between the second outer conductor and the central conductor, a third outer conductor (51) arranged between the first outer conductor and the second outer conductor coaxially with the central conductor, and a third dielectric body (52) filled between the third outer conductor and the central conductor.

Abstract: An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE?the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

Abstract: A driver circuit 11 includes a plurality of cascode-connected NMOS transistors, a modulating signal VGN1 is applied to a gate terminal of a lowermost stage transistor TN1 located at a lowermost stage out of the NMOS transistors, and an upper stage bias potential VGN2 that is a sum of a minimum gate-source voltage VGN1min and a maximum drain-source voltage VDS1max of a transistor (TN1) located immediately below an upper stage transistor located at an upper stage above the lowermost stage transistor of the NMOS transistors is applied to the upper stage transistor TN2.

Abstract: An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.