Abstract: An embodiment includes an output circuit with transistors and a withstand voltage protection circuit. The withstand voltage protection circuit includes resistors connected between an output signal terminal on the positive phase side and an output signal terminal on the negative phase side. A switch includes an NMOS transistor having a gate terminal connected to the connection point of the resistors, a drain terminal connected to the bias voltage, and a source terminal connected to the base terminal of the transistor.

Abstract: A plurality of waveguide structures are loaded on a top surface opposed to a bottom surface of a metal case, on which a high-frequency circuit is mounted, a height, a width, and a length of each of the plurality of waveguide structures have dimensions corresponding to a quarter-wave of a cutoff frequency indicating a frequency band of a target electromagnetic wave to be blocked, and a width and a length of each of the plurality of waveguide structures have dimensions that allow only a high-frequency wave of a mode to propagate in the frequency band.

Abstract: The driver circuit includes DC cut capacitors, an input buffer, input termination resistors connected in series between differential input signal terminals and an ESD protection circuit connected to a connection point of the input terminal resistors. The ESD protection circuit includes diodes.

Abstract: A thin-film resistive element includes: a first electrode that is formed with a conductor formed in an annular shape in a planar view; a second electrode that is formed with a conductor disposed at a distance from the first electrode in a region surrounded by the first electrode; and a thin-film resistor that is electrically connected to the first electrode and the second electrode.

Abstract: An embodiment is a distributed amplifier including amplifier blocks, each of the amplifier blocks including a first transmission line to receive input of a signal to an input end, a second transmission line to output a signal from an output end, a first termination resistor having a first end connected to a terminal end of the first transmission line, a second termination resistor having a first end connected to an input end of the second transmission line, and unit cells arranged along the first and second transmission lines, each of the unit cells having an input terminal connected to the first transmission line and an output terminal connected to the second transmission line, the amplifier blocks are connected in cascade such that a terminal end of the second transmission line of one of the amplifier blocks is connected to the first transmission line of a subsequent amplifier block.

Abstract: An embodiment is a multiplexer including a first distributed amplifier with an impedance matched to 50?, the first distributed amplifier configured to receive a first signal and output a first amplified signal, a second distributed amplifier with an impedance matched to 50?, the second distributed amplifier configured to receive a second signal and output a second amplified signal, and a passive multiplexer configured to multiplex the first amplified signal and the second amplified signal, and output a multiplexed signal to a signal output terminal, the passive multiplexer including a first resistor having a first end to receive the first amplified signal, a second resistor having a first end to receive the second amplified signal, and a third resistor having a first end connected to second ends of the first and second resistors and a second end connected to the signal output terminal.

Abstract: A first phase adjuster adjusts the phase of any one of first and second AC voltages generated in a negative resistance circuit so that a shift amount ? in a first variable phase shifter falls within a range of 0 degrees??<180 degrees, and outputs the phase-adjusted AC voltage to the first variable phase shifter, and a second phase adjuster adjusts the phase of the other one of the first and second AC voltages generated in the negative resistance circuit so that a shift amount ? in a second variable phase shifter falls within a range of 0 degrees??<180 degrees, and outputs the phase-adjusted AC voltage to the second variable phase shifter.

Abstract: An amplifier circuit includes source-grounded amplifiers and a neutralization circuit that is connected between drain terminals and gate terminals of the source-grounded amplifiers and neutralizes a feedback capacitance of the source-grounded amplifiers, and the neutralization circuit includes transmission lines and a capacitor connected in series.

Abstract: A predriver includes a first transistor for receiving a signal at a gate thereof, a load resistance, a first peaking inductor, a second peaking inductor, a second transistor for receiving a control voltage at a gate thereof, a third transistor for receiving a control voltage at a gate thereof, an inductor for suppressing the group delay, a first peaking capacitor, a second peaking capacitor, and a peaking resistance.

Abstract: Bias adjusting circuits (1_(2k-1), 1_2k) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (2N-2k+1):(2k-1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (2_1 to 2_2N).

Abstract: A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.

Abstract: Stub conductors are disposed so as to surround an outer periphery of a patch conductor and be spaced from the patch conductor with a gap positioned between the stub conductors and the patch conductor.

Abstract: A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.

Abstract: A permittivity measuring method includes measuring a set of phases at sampling frequencies of at least three points in each of a first-half portion and a second-half portion of a phase characteristic of electromagnetic waves that passed through a measurement target, if the mode of the phase changes of both sets of phases belongs to a phase group in which change of the at least three points in the first half and change of at least three points in the second half are both monotonic change, maximal values, or minimal values, calculating the permittivity using the phase slope of the phases in the first-half portion and the phases in the second-half portion, and if the mode of the phase changes does not belong to the phase group, calculating the permittivity by fitting the phases of either the first half or the second half to a quadratic function.

Abstract: A negative feedback inductor and a gate inductor are formed in different wiring layers of a substrate so as to be at least partially overlapped with each other in a plan view. When the lower wiring layer is thinner and the upper wiring layer is thicker, the negative feedback inductor Lc is formed in the lower wiring layer that is thinner.

Abstract: A driver circuit includes a differential pair of transistors that amplify differential input signals and output the amplified differential input signals from signal output terminals, a current source that supplies a constant current to the differential pair of transistors, a switch that stops the current supply from the current source to the differential pair of transistors during a shutdown mode period, capacitors each having one end connected to the ground, a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during an amplification mode period, and a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during the amplification mode period.

Abstract: A distributed amplifier includes a transmission line configured so as to transmit a signal, a variable capacitor having one end connected to the transmission line and the other end connected to the ground, and configured so that the capacitance is adjustable, and a variable capacitor having one end connected to the transmission line and the other end connected to the ground, and configured so that the capacitance is adjustable. The transmission line is configured in such a manner that the inductance is adjustable.

Abstract: A distributed amplifier includes: a transmission line having an input end that an input signal is input to; a transmission line having an output end that an output signal is output from; an input termination resistor connected to an end terminal of the transmission line; a plurality of unit cells arranged along the transmission lines, and having input terminals connected to the transmission line and output terminals connected to the transmission line; and a variable current source having one end connected to the end terminal of the transmission line and another end connected to a power supply voltage, and capable of adjusting a current amount between the transmission line and the power supply voltage.

Abstract: Arranged on a surface of a substrate are a patch conductor that radiates an electromagnetic field having been fed, a feed line that feeds the patch conductor with the electromagnetic field having been input, two slits parallel to the feed line on both sides of a connection part of the feed line toward an inner side of the patch conductor, and a ring conductor at a space from the patch conductor with an interposition of a gap to surround an outer periphery of the patch conductor. Accordingly, an electric capacitance can be formed between the patch conductor and the ring conductor, and when achieving impedance matching with the feed line, adjustment can be performed using the size of the ring conductor and the gap.

Abstract: In a distributed amplifier, a plurality of cascode amplifiers connected in parallel between an input side transmission line and an output side transmission line are provided, a transmission line is connected to an input terminal of an output transistor of each of the amplifiers, and a bias potential is applied from a bias circuit to the input terminal of the output transistor via the transmission line.