Patents by Inventor Hideyuki Sugiyama
Hideyuki Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150357016Abstract: A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.Type: ApplicationFiled: August 21, 2015Publication date: December 10, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Mizue ISHIKAWA, Hideyuki SUGIYAMA, Yoshiaki SAITO, Tetsufumi TANAMOTO
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Publication number: 20150311305Abstract: An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mizue ISHIKAWA, Tomoaki INOKUCHI, Hideyuki SUGIYAMA, Tetsufumi TANAMOTO, Yoshiaki SAITO
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Patent number: 9112131Abstract: A spin MOSFET includes a first ferromagnetic layer having a fixed magnetization direction, a first tunnel barrier, a second ferromagnetic layer having a variable magnetization direction, and a nonmagnetic semiconductor layer provided in that order on a substrate. The nonmagnetic semiconductor layer has lower and upper faces and a side faces serving as a channel. A third ferromagnetic layer having a fixed magnetization direction is provided on the upper face of the nonmagnetic semiconductor layer, wherein the magnetization direction of each of the first to third ferromagnetic layers is in parallel or antiparallel to a direction from the third ferromagnetic layer to the first ferromagnetic layer. A nonmagnetic layer is provided on the third ferromagnetic layer, and a gate insulating film and gate electrode are provided in that order on the side face of the nonmagnetic semiconductor layer.Type: GrantFiled: December 13, 2013Date of Patent: August 18, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
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Patent number: 9112139Abstract: A spin transistor according to an embodiment includes: a first magnetic layer formed above a substrate and serving as one of a source and a drain; an insulating film having a lower face facing to an upper face of the first magnetic layer, an upper face opposed to the lower face, and a side face different from the lower and upper faces, the insulating film being formed on the upper face of the first magnetic layer and serving as a channel; a second magnetic layer formed on the upper face of the insulating film and serving as the other one of the source and the drain; a gate electrode formed along the side face of the insulating film; and a gate insulating film located between the gate electrode and the side face of the insulating film.Type: GrantFiled: June 18, 2012Date of Patent: August 18, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki Inokuchi, Takao Marukame, Tetsufumi Tanamoto, Hideyuki Sugiyama, Mizue Ishikawa, Yoshiaki Saito
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Publication number: 20150111095Abstract: A lithium-ion battery includes: a power generation element having a structure where a positive electrode and a negative electrode are stacked with a separator interposed therebetween; a positive-electrode current collector connected to the positive electrode; a negative-electrode current collector connected to the negative electrode; a shrink tube bundling the power generation element, the positive-electrode current collector, and the negative-electrode current collector together; a non-aqueous electrolyte; and a battery case housing the power generation element, the positive-electrode current collector, the negative-electrode current collector, the shrink tube, and the non-aqueous electrolyte, wherein the positive-electrode current collector and the negative-electrode current collector are fixed to the battery case, and the shrink tube is a seamless tube.Type: ApplicationFiled: May 22, 2013Publication date: April 23, 2015Applicant: ELIIY Power Co., Ltd.Inventors: Michito Sato, Hideyuki Sugiyama
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Patent number: 8981436Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.Type: GrantFiled: September 30, 2013Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Tetsufumi Tanamoto
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Patent number: 8958239Abstract: One embodiment provides a magnetic memory element, including: a first ferromagnetic layer whose magnetization is variable; a second ferromagnetic layer which has a first band split into a valence band and a conduction band and a second band being continuous at least from the valence band to the conduction band; and a nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer.Type: GrantFiled: June 26, 2012Date of Patent: February 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Hideyuki Sugiyama, Masahiko Nakayama, Tatsuya Kishi, Hiroaki Yoda, Yoshiaki Saito
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Publication number: 20140301136Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.Type: ApplicationFiled: March 11, 2014Publication date: October 9, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Mizue ISHIKAWA, Hideyuki SUGIYAMA, Tetsufumi TANAMOTO, Akira TAKASHIMA, Yoshiaki SAITO
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Publication number: 20140291744Abstract: A spin FET of an aspect of the present invention includes source/drain regions, a channel region between the source/drain regions, and a gate electrode above the channel region. Each of the source/drain regions includes a stack structure which is comprised of a low work function material and a ferromagnet. The low work function material is a non-oxide which is comprised of one of Mg, K, Ca and Sc, or an alloy which includes the non-oxide of 50 at % or more.Type: ApplicationFiled: June 10, 2014Publication date: October 2, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiaki SAITO, Hideyuki Sugiyama, Tomoaki Inokuchi, Mizue Ishikawa
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Patent number: 8847288Abstract: A spin transistor according to an embodiment includes: a semiconductor layer including a p+-region and an n+-region located at a distance from each other, and an i-region located between the p+-region and the n+-region; a first electrode located on the p+-region, the first electrode including a first ferromagnetic layer; a second electrode located on the n+-region, the second electrode including a second ferromagnetic layer; and a gate located on at least the i-region.Type: GrantFiled: January 25, 2013Date of Patent: September 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
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Patent number: 8779496Abstract: A spin FET includes a first ferromagnetic film disposed on a first source/drain area, a direction of magnetization thereof being fixed in an upward direction or a downward direction perpendicular to a film surface, a second ferromagnetic film disposed on a second source/drain area, a direction of magnetization thereof being changed in the upward direction or the downward direction, an anti-ferromagnetic ferroelectric film disposed on the second ferromagnetic film, and a tunnel barrier film disposed at least between the first source/drain area and the first ferromagnetic film or between the second source/drain and the second ferromagnetic film. Resistance of the anti-ferromagnetic ferroelectric film is larger than ON resistance when the first and second source/drain areas conduct electricity through the channel area.Type: GrantFiled: February 11, 2008Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
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Publication number: 20140117427Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.Type: ApplicationFiled: September 30, 2013Publication date: May 1, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiaki SAITO, Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Tetsufumi Tanamoto
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Publication number: 20140097474Abstract: A spin MOSFET includes a first ferromagnetic layer having a fixed magnetization direction, a first tunnel barrier, a second ferromagnetic layer having a variable magnetization direction, and a nonmagnetic semiconductor layer provided in that order on a substrate. The nonmagnetic semiconductor layer has lower and upper faces and a side faces serving as a channel. A third ferromagnetic layer having a fixed magnetization direction is provided on the upper face of the nonmagnetic semiconductor layer, wherein the magnetization direction of each of the first to third ferromagnetic layers is in parallel or antiparallel to a direction from the third ferromagnetic layer to the first ferromagnetic layer. A nonmagnetic layer is provided on the third ferromagnetic layer, and a gate insulating film and gate electrode are provided in that order on the side face of the nonmagnetic semiconductor layer.Type: ApplicationFiled: December 13, 2013Publication date: April 10, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
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Patent number: 8637946Abstract: A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.Type: GrantFiled: September 9, 2011Date of Patent: January 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa
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Patent number: 8618590Abstract: A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.Type: GrantFiled: September 17, 2009Date of Patent: December 31, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
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Patent number: 8611143Abstract: A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode.Type: GrantFiled: February 23, 2012Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Sugiyama, Masato Oda, Shinobu Fujita, Tetsufumi Tanamoto, Mizue Ishikawa, Takao Marukame, Tomoaki Inokuchi, Yoshiaki Saito
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Patent number: 8592454Abstract: The present invention relates to a compound represented by the formula wherein ring A is a nitrogen-containing heterocycle; ring B is an aromatic ring optionally having substituent(s); ring D is an aromatic ring optionally having substituent(s); L is a group represented by the formula R2, R3, R4a and R4b are each independently a hydrogen atom, an optionally halogenated C1-6 alkyl group or an optionally halogenated C3-6 cycloalkyl group, or R2 and R3 are optionally bonded via an alkylene chain or an alkenylene chain, or R4a and R4b are optionally bonded via an alkylene chain or an alkenylene chain; R1 is a hydrogen atom or a substituent; m and n are each independently an integer of 0 to 5; m+n is an integer of 2 to 5; and is a single bond or double bond, or a salt thereof; and the like.Type: GrantFiled: September 18, 2009Date of Patent: November 26, 2013Assignee: Takeda Pharmaceutical Company LimitedInventors: Junya Shirai, Hideyuki Sugiyama, Taku Kamei, Hironobu Maezaki
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Patent number: 8576601Abstract: One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.Type: GrantFiled: February 23, 2012Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takao Marukame, Tomoaki Inokuchi, Hideyuki Sugiyama, Mizue Ishikawa, Yoshiaki Saito, Atsuhiro Kinoshita, Kosuke Tatsumura
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Publication number: 20130248941Abstract: A spin transistor according to an embodiment includes: a semiconductor layer including a p+-region and an n+-region located at a distance from each other, and an i-region located between the p+-region and the n+-region; a first electrode located on the p+-region, the first electrode including a first ferromagnetic layer; a second electrode located on the n+-region, the second electrode including a second ferromagnetic layer; and a gate located on at least the i-region.Type: ApplicationFiled: January 25, 2013Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
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Patent number: 8487359Abstract: It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.Type: GrantFiled: June 18, 2009Date of Patent: July 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi, Mizue Ishikawa, Takao Marukame