Abstract: A device for supporting deterioration determination includes: a first calculating unit that: acquires a dataset including a plurality of reaction condition values and a voltage in a first period and in a second period; and uses the dataset and a calculation formula to calculate a parameter group of the calculation formula for each period; a second calculating unit that substitutes a reaction condition value in the calculation formula in which the parameter group is incorporated to calculate a comparison target value for each period; and a third calculating unit that calculates a deterioration degree of the water electrolysis module based on a difference between a first comparison target value and a second comparison target value.

Abstract: A positive electrode mixture layer for a lithium-ion secondary battery suitable for producing a lithium-ion secondary battery with high rate characteristics at an ordinary temperature and low temperatures and low internal resistance (DCR) at low temperatures, characterized by including a positive electrode active material, a binder, and a conductive additive, in which the conductive additive includes carbon black, a carbon nanotube (1) having an average fiber diameter of 80 to 400 nm, and a carbon nanotube (2) having an average fiber diameter of 0.4 to 3.0 nm, the content rates of the carbon black, the carbon nanotube (1), and the carbon nanotube (2) in the conductive additive are 40 to 80% by mass, 10 to 50% by mass, and 1 to 30% by mass, respectively, and the content rate of the conductive additive in the positive electrode mixed layer is 0.1 to 5.0% by mass.

Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.

Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.

Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.

Abstract: A method of manufacturing a semiconductor device includes forming a base layer in an upper part of a substrate and a trench in the substrate. A gate insulating film is on an inner bottom surface and an inner side surface of the trench and a gate electrode is embedded into the trench. The gate electrode is etched so that an upper surface of the gate electrode is at a first height from the bottom of the trench. A source region is in contact with an outer side surface of the trench. A base contact region is in contact with part of the outer side surface of the trench, an upper part of the base layer, and an upper part of the source region. A source electrode is embedded in a remaining part of the trench and in contact with the source region and the base contact region.

Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.

Abstract: A method of manufacturing a semiconductor device includes forming a base layer in an upper part of a substrate and a trench in the substrate. A gate insulating film is on an inner bottom surface and an inner side surface of the trench and a gate electrode is embedded into the trench. The gate electrode is etched so that an upper surface of the gate electrode is at a first height from the bottom of the trench. A source region is in contact with an outer side surface of the trench. A base contact region is in contact with part of the outer side surface of the trench, an upper part of the base layer, and an upper part of the source region. A source electrode is embedded in a remaining part of the trench and in contact with the source region and the base contact region.

Abstract: Provided is a semiconductor device having an ESD protection diode and a vertical MOSFET in which desired ESD tolerance is obtained without reducing the active region size or increasing the chip size. The semiconductor device includes: a substrate; a drain region and a source region in the substrate; a base region between the drain region and the source region; a gate electrode comprising a first polysilicon layer, and being in contact with the base region across a gate insulating film so that a channel is formed in the base region; and a bidirectional diode in which the gate electrode, a second polysilicon layer, and a third polysilicon layer are arranged in the stated order in a direction perpendicular to a front surface of the substrate.

Abstract: A semiconductor device includes: a drain region formed on a rear surface side of a substrate; a base layer formed between the drain region and a front surface of the substrate; a trench formed in the substrate; a gate insulating film covering an inner surface of the trench from a bottom of the trench to a first height; a gate electrode filling the trench to the first height; an insulating film filling the trench to a second height higher than the first height; a source electrode filling a remaining part of the trench; a base contact region formed in a surface of the substrate and has one side contacting the source electrode; and a source region having an upper surface contacting a part of a bottom surface of the base contact region, one side contacting a side of the trench and is partially contacting the source electrode.

Abstract: Provided is a semiconductor device having an ESD protection diode and a vertical MOSFET in which desired ESD tolerance is obtained without reducing the active region size or increasing the chip size. The semiconductor device includes: a substrate; a drain region and a source region in the substrate; a base region between the drain region and the source region; a gate electrode comprising a first polysilicon layer, and being in contact with the base region across a gate insulating film so that a channel is formed in the base region; and a bidirectional diode in which the gate electrode, a second polysilicon layer, and a third polysilicon layer are arranged in the stated order in a direction perpendicular to a front surface of the substrate.

Abstract: A semiconductor device includes: a drain region formed on a rear surface side of a substrate; a base layer formed between the drain region and a front surface of the substrate; a trench formed in the substrate; a gate insulating film covering an inner surface of the trench from a bottom of the trench to a first height; a gate electrode filling the trench to the first height; an insulating film filling the trench to a second height higher than the first height; a source electrode filling a remaining part of the trench; a base contact region formed in a surface of the substrate and has one side contacting the source electrode; and a source region having an upper surface contacting a part of a bottom surface of the base contact region, one side contacting a side of the trench and is partially contacting the source electrode.

Abstract: A semiconductor integrated circuit device capable of stably forming a fuse element that is used to adjust the characteristics of the semiconductor integrated circuit device, and a method of manufacturing the semiconductor integrated circuit device are provided. The thickness of an interlayer insulating film above the fuse element is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The steady ease of laser trimming processing is thus accomplished in the semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device.

Abstract: Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.

Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.

Abstract: A semiconductor integrated circuit device capable of stably forming a fuse element that is used to adjust the characteristics of the semiconductor integrated circuit device, and a method of manufacturing the semiconductor integrated circuit device are provided. The thickness of an interlayer insulating film above the fuse element is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The steady ease of laser trimming processing is thus accomplished in the semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device.

Abstract: A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range.

Abstract: A semiconductor integrated circuit device includes a fuse element that can be laser trimmed to adjust the characteristics of the semiconductor integrated circuit device, The semiconductor integrated circuit device includes an interlayer insulating film above the fuse element, and the thickness of the interlayer insulating film is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The laser trimming processing is thus stabilized without needing a high level of dry etching stabilization control.

Abstract: A semiconductor integrated circuit device includes a PMOS output element having a source electrode connected to a power supply terminal and a drain electrode connected to an output voltage terminal from which an output voltage is supplied. A voltage dividing circuit has resistors for dividing the supplied output voltage to produce a divided voltage. A reference voltage circuit generates a reference voltage and has a memory element whose threshold voltage determines the reference voltage. The reference voltage circuit has a regulating input terminal connected to the memory element to change the threshold voltage of the memory element. An error amplifier is supplied with the divided voltage and the reference voltage to generate a voltage that is applied to a gate electrode of the PMOS output element. The voltage is amplified depending on a difference between the divided voltage and the reference voltage.

Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.