Patents by Inventor Hirofumi Harada

Hirofumi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030204841
    Abstract: The present invention is intended to provide a program management system for, upon activation of a program updating operation, automatically performing according to a mode selected by preparing plural kinds of program updating modes and previously selecting one of them.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Rintaro Nakane, Osamu Tachiyama, Kazuo Sumioka, Seiya Shimizu, Shuichi Tsujimoto, Masanori Kawasumi, Yoshito Nakanishi, Yaeko Harada, Masayuki Fukusawa, Hirofumi Harada
  • Patent number: 6624469
    Abstract: There is provided a vertical MOS transistor in which a high frequency characteristic is improved, a low voltage operation is realized, and a stable characteristic with less fluctuation is obtained. After trench gate oxidation, a body is formed at a side wall by inclined ion implantation, and after formation of a gate electrode, a low concentration source region is formed by inclined ion implantation, so that a capacitance between a gate and a source and a capacitance between a gate and a drain are suppressed. When the above body region formation method is used, an impurity distribution between the drain and the source of a channel region also becomes uniform. Besides, since a channel length is determined by an etching apparatus, by using the same apparatus for trench-etching and for etching of the gate electrode, a stable channel length can be obtained.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: September 23, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Hirofumi Harada
  • Publication number: 20030154145
    Abstract: A membership information integrated management system comprising a target server, and a membership server that is connected to the target server and that requires a membership registration, wherein
    Type: Application
    Filed: December 31, 2002
    Publication date: August 14, 2003
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Hiroshi Yamamoto, Hiroshi Yamaguchi, Katsuo Shioiri, Hirofumi Harada, Keishi Higashi, Mitsuya Sato
  • Patent number: 6570229
    Abstract: An insulated gate N-channel field effect transistor has a P-type semiconductor substrate, an N-type epitaxial layer disposed on the P-type semiconductor substrate, and a gate insulating film disposed on the N-type epitaxial layer. An N-type high concentration source region is formed in the N-type epitaxial layer. An N-type high concentration drain region is formed in the epitaxial layer in spaced-apart relation to the N-type high concentration source region. A channel forming region is disposed between the N-type high concentration source region and the N-type high concentration drain region. A gate electrode is formed on the channel forming region through the gate insulating film. An N-type low concentration region is disposed between the N-type high concentration drain region and the channel forming region and between the N-type high concentration source region and the channel forming region. An insulating film is disposed on the low concentration region.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: May 27, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Hirofumi Harada
  • Publication number: 20030093490
    Abstract: There is provided an information storage output system enhanced in mobility and improved in convenience to use. In the information storage output system for storing predetermined storage data in a storage server on a network, the storage server can be accessed from many and unspecified communication devices. The information storage output system includes a plurality of remote output terminals for outputting supply data supplied via a network in a predetermined output form, a remote output server having a function of supplying at least the supply data to one of the remote output terminals, and an output request communication terminal for transmitting a primary output request of the storage data to the storage server or the remote output server via a network. The storage data is output from the remote output terminal in response to the primary output request transmitted from the output request communication terminal.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 15, 2003
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Hiroshi Yamamoto, Hiroshi Yamaguchi, Tsunehiro Motegi, Katsuo Shioiri, Hirofumi Harada, Keishi Higashi, Mitsuya Sato
  • Publication number: 20030080382
    Abstract: In a BiCMOS integrated circuit, without increasing steps and a circuit area, a high transistor having high withstand voltage and high ESD strength is provided.
    Type: Application
    Filed: November 27, 2002
    Publication date: May 1, 2003
    Applicant: SEIKO INSTRUMENTS INC.
    Inventors: Hirofumi Harada, Jun Osanai
  • Publication number: 20030074597
    Abstract: A service center judges parts required for repair according to the trouble information received from a multi-functional peripheral (MFP), searches servicemen carrying repair parts based on the contents of the serviceman carrying parts memory, and contacts a portable terminal carried by an applicable servicemen. Then, by grasping the condition of the serviceman, e.g., whether he is in working, traveling or taking a rest, stores the condition of servicemen in the serviceman condition memory. In succession, based on the contents of the serviceman positioning memory, the serviceman condition memory and the MFP installation place memory, the service center searches a serviceman who is able to go most fast to the installing place of a MFP to be repaired among servicemen who carry required repair parts, and gives a repair direction to a portable terminal carried by this searched serviceman together the installing place of the MFP and contents of the trouble.
    Type: Application
    Filed: September 23, 2002
    Publication date: April 17, 2003
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Hirofumi Harada, Ichiro Hase, Toshiyuki Oda, Yaeko Harada, Kei Kato, Leonhard Gelbrich
  • Patent number: 6525376
    Abstract: A high withstand voltage insulated gate N-channel field effect transistor has a P-type semiconductor substrate and an N-type epitaxial layer formed on the semiconductor substrate. An N-type source region having a high concentration is formed on the epitaxial layer. An N-type drain region having a high concentration is formed on the epitaxial layer and is spaced-apart from the source region. A channel forming region is disposed between the source region and the drain region. A gate insulating film is disposed over the source and drain regions and the channel forming region. A gate electrode is formed through the channel forming region and the gate insulating film. An N-type low concentration region is formed between the drain region and the channel forming region. A second insulating film is formed on the low concentration region and has a thickness greater than that of the gate insulating film.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: February 25, 2003
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6511885
    Abstract: There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p− epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p− epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: January 28, 2003
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Publication number: 20020193097
    Abstract: An electronic catalog system sends catalog address information to a mobile phone through a wireless communication, sends catalog data adaptable to address information selected by the mobile phone to a storage server, and prints and outputs catalog data stored in the storage server.
    Type: Application
    Filed: April 24, 2002
    Publication date: December 19, 2002
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Hiroshi Yamaguchi, Hirofumi Harada, Hiroshi Shintani, Aya Inokuchi, Akinori Iwase, Kazuhiro Ogura, Miho Inahara
  • Patent number: 6495884
    Abstract: There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p− epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p− epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: December 17, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Publication number: 20020158277
    Abstract: In a semiconductor integrated circuit device in which the number of the PMOS transistors to be used is relatively larger than that of the NMOS transistors and the PMOS transistor is used as an output driver, there is provided a semiconductor integrated circuit device having excellent stability, reliability, and performance while being inexpensive, and a manufacturing method thereof. In such a semiconductor integrated circuit device, complementary MOS circuits are composed of a P-type MOSFET (36) and an N-type MOSFET (37) which are a horizontal, an output driver is composed of a P-type vertical MOSFET (38) having a trench structure, and a conductivity type of the gate electrode of the respective MOSFETs is set as a P-type.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 31, 2002
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6426258
    Abstract: A method of manufacturing a semiconductor integrated circuit device comprises forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a polycrystal silicon film on the gate insulating film, etching the polycrystal silicon film to form a gate electrode on a portion of the gate insulating film, etching the gate insulating film except at the portion thereof where the gate electrode has been formed, and forming a thermal oxide film on the semiconductor substrate at regions corresponding to the etched gate insulating film. Impurities of a second conductivity type are implanted into a source region in the semiconductor substrate through the thermal oxide film to form a body region of the second conductivity type. The semiconductor substrate is then heated at a temperature of 1000° C. or higher.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: July 30, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Publication number: 20020000608
    Abstract: Disclosed are a vertical MOS transistor which lowers the gate resistance, improves the high frequency characteristics, and improves the yield compared with a conventional one and a method of manufacturing the same. When gate voltage is applied to a gate electrode, a channel is formed in a body region along a trench, and electrons or current flow(s) from a drain layer to a source layer. Here, a gate in the trench has a laminated structure of a polycrystalline silicon film and a metal silicide. Therefore, a gate resistance is lowered and the high frequency characteristics are improved. Further, according to the structure and the method of manufacturing, a concave portion generated at an upper portion of the gate in the trench when etching for forming the gate is less liable to be generated, and thus, malfunction and insufficient reliability due to the concave portion can be avoided.
    Type: Application
    Filed: June 2, 2001
    Publication date: January 3, 2002
    Inventor: Hirofumi Harada
  • Publication number: 20010025986
    Abstract: There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p− epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p− epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved.
    Type: Application
    Filed: January 23, 2001
    Publication date: October 4, 2001
    Inventors: Hirofumi Harada, Jun Osanai
  • Publication number: 20010023959
    Abstract: There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p- epitaxial growth layer along a trench, and an electron current flows from an n+drain layer to the p- epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved.
    Type: Application
    Filed: January 23, 2001
    Publication date: September 27, 2001
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6236084
    Abstract: To provide a lateral double diffusion insulated gate field effect transistor with high driving current and low source-drain withstand voltage without receiving the influence of process fluctuation. Without shortening a gate electrode 10 as compared with conventional one, an impurity of the same conductivity type as a drain is ion-implanted from the side of a high concentration drain region 20 by using the gate electrode as a mask in a self-aligning manner. The amount of impurity implantation is set as higher than the concentration of a semiconductor substrate 19.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: May 22, 2001
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6013940
    Abstract: A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: January 11, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai, Yoshikazu Kojima, Yutaka Saitoh
  • Patent number: 6005275
    Abstract: A semiconductor device comprises a semiconductor acceleration sensor having a cantilever made of a semiconductor material, a supporter for supporting the cantilever, and diffused resistors disposed on the cantilever. An acceleration detecting device detects a displacement of the cantilever based on acceleration forces applied to the cantilever and on changes of resistance values of the diffused resistors.
    Type: Grant
    Filed: August 23, 1995
    Date of Patent: December 21, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Masataka Shinogi, Yutaka Saitoh, Yoshifumi Yoshida, Hirofumi Harada, Kenji Katoh
  • Patent number: 5959343
    Abstract: A semiconductor device comprises a reference voltage device for outputting a constant voltage, a voltage dividing device receptive of the constant voltage for dividing the constant voltage and outputting different currents, a digital signal processing device receptive of the different currents outputted by the voltage dividing device and outputting voltages, and a voltage amplifying device receptive of at least a ground voltage and one of the voltages outputted by the digital signal processing device and outputting a signal produced by amplifying the voltage of the digital signal processing device.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: September 28, 1999
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Hirofumi Harada, Yutaka Saitoh