Patents by Inventor Hirofumi Harada

Hirofumi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7228339
    Abstract: There is provided an information storage output system enhanced in mobility and improved in convenience to use. In the information storage output system for storing predetermined storage data in a storage server on a network, the storage server can be accessed from many and unspecified communication devices. The information storage output system includes a plurality of remote output terminals for outputting supply data supplied via a network in a predetermined output form, a remote output server having a function of supplying at least the supply data to one of the remote output terminals, and an output request communication terminal for transmitting a primary output request of the storage data to the storage server or the remote output server via a network. The storage data is output from the remote output terminal in response to the primary output request transmitted from the output request communication terminal.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: June 5, 2007
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventors: Hiroshi Yamamoto, Hiroshi Yamaguchi, Tsunehiro Motegi, Katsuo Shioiri, Hirofumi Harada, Keishi Higashi, Mitsuya Sato
  • Publication number: 20070023844
    Abstract: Provided is a method capable of forming a polycrystalline silicon resistor with preferable ratio accuracy so as to design a resistor circuit with high accuracy. In the method, a length of a low concentration impurity region constituting the polycrystalline silicon resistor in a longitudinal direction is varied in accordance with an occupying area of a metal portion overlapping the low concentration impurity region, thereby correcting a variation in resistance without varying an external shape and the occupying area of the resistor.
    Type: Application
    Filed: July 26, 2006
    Publication date: February 1, 2007
    Inventors: Akiko Tsukamoto, Hirofumi Harada
  • Publication number: 20070006216
    Abstract: The present invention is intended to provide a program management system for, upon activation of a program updating operation, automatically performing according to a mode selected by preparing plural kinds of program updating modes and previously selecting one of them. There is disclosed a program management apparatus adapted to perform a program updating operation of a program by downloading the program from a server which manages an information of the program to a predetermined terminal device, comprising: pattern setting means, which retains plural kinds of patterns each serving as a mode for giving an information inclusive of a program and updating such a program, for allowing a user to select one of the patterns so as to previously set it as a selected pattern; and program updating means for, upon activation of a program updating operation, automatically performing said program updating operation according to said selected pattern set by said pattern setting means.
    Type: Application
    Filed: August 17, 2006
    Publication date: January 4, 2007
    Inventors: Rintaro Nakane, Osamu Tachiyama, Kazuo Sumioka, Seiya Shimizu, Shuichi Tsujimoto, Masanori Kawasumi, Yoshito Nakanishi, Yaeko Harada, Masayuki Fukusawa, Hirofumi Harada
  • Publication number: 20060292764
    Abstract: In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. An intermediate insulating film is deposited over a main surface of the semiconductor substrate and the gate electrode. The intermediate insulating film overlying the main surface of the semiconductor substrate is then etched back so as to entirely expose the source region and the body contact region. A source metal electrode is formed over the main surface of the semiconductor substrate so as to cover the source region and body contact region.
    Type: Application
    Filed: August 30, 2006
    Publication date: December 28, 2006
    Inventor: Hirofumi Harada
  • Publication number: 20060214235
    Abstract: A Plurality of resistor groups composed of polycrystalline silicon resistors constitutes a resistor circuit. A plurality of metal portions each having the same area is formed above each of the resistor groups to make the influence of external disturbances on the metal portions in a semiconductor process uniform, and thus reducing resistance fluctuation in the polycrystalline silicon resistors.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 28, 2006
    Inventor: Hirofumi Harada
  • Patent number: 7100158
    Abstract: There is provided a program management apparatus adapted to perform a program updating operation of a program by downloading the program from a server which manages an information of the program to a predetermined terminal device, including: a pattern setting unit, which retains plural kinds of patterns each serving as a mode for giving an information inclusive of a program and updating such a program, for allowing a user to select one of the patterns so as to previously set it as a selected pattern; and a program updating unit for, upon activation of a program updating operation, automatically performing the program updating operation according to the selected pattern set by the pattern setting unit.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: August 29, 2006
    Assignee: Toshiba TEC Kabushiki Kaisha
    Inventors: Rintaro Nakane, Osamu Tachiyama, Kazuo Sumioka, Seiya Shimizu, Shuichi Tsujimoto, Masanori Kawasumi, Yoshito Nakanishi, Yaeko Harada, Masayuki Fukusawa, Hirofumi Harada
  • Patent number: 7034359
    Abstract: A vertical MOS transistor has a high concentration drain region, a low concentration drain region disposed on the high concentration drain region, a body region disposed on the low concentration drain region, a high concentration body contact region disposed on the body region, and a high concentration source region formed on a portion of the body region outside of the high concentration body contact region. A first silicon trench passes through the body region and the high concentration source region and extends into the low concentration drain region. A second silicon trench is disposed in contact with the high concentration body contact region but not in contact with the high concentration source region. A gate insulator film is formed in each of the first and second silicon trenches. High concentration polycrystalline silicon gates are embedded within the respective first and second trenches and are surrounded by the gate insulator film.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: April 25, 2006
    Assignee: Seiko Instruments Inc.
    Inventor: Hirofumi Harada
  • Publication number: 20060027894
    Abstract: Polycrystalline silicon resistors are covered with a metal wiring connected to one of terminals of a resistor circuit in order to provide a stable resistor circuit, and a variation in resistance owing to a resultant potential difference between the metal wiring and the resistor is cancelled by gradually changing the length of low concentration impurity region and high concentration impurity region of the respective resistor that constitutes the resistor circuit.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 9, 2006
    Inventor: Hirofumi Harada
  • Patent number: 6993526
    Abstract: An electronic catalog system sends catalog address information to a mobile phone through a wireless communication, sends catalog data adaptable to address information selected by the mobile phone to a storage server, and prints and outputs catalog data stored in the storage server.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: January 31, 2006
    Assignee: Toshiba Tec Kabushika Kaisha
    Inventors: Hiroshi Yamaguchi, Hirofumi Harada, Hiroshi Shintani, Aya Inokuchi, Akinori Iwase, Kazuhiro Ogura, Miho Inahara
  • Publication number: 20060006470
    Abstract: A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bidirectional diode. The bi-directional diode connects a gate electrode with the semiconductor substrate in the depletion-type MOS field-effect transistor through metal wirings.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 12, 2006
    Inventor: Hirofumi Harada
  • Patent number: 6921949
    Abstract: A semiconductor integrated circuit device is comprised of an amplifier circuit having first and second PMOS and NMOS transistors. The first PMOS transistor has a gate electrode and a drain electrode connected together. The second PMOS transistor has a gate electrode connected to the gate electrode of the first PMOS transistor and a course electrode connected to a course electrode of the first PMOS transistor. The first NMOS transistor has a drain electrode connected to the drain electrode of the first PMOS transistor and a gate electrode sat as a first input terminal. The second NMOS transistor has a drain electrode connected to a drain electrode of the second PMOS transistor, a source electrode connected to a sourse electrode of the first NMOS transistor, and a gate electrode sat as a second input terminal. At least one of the first NMOS transistor and the second NMOS transistor is comprised of a buried channel transistor.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: July 26, 2005
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6844578
    Abstract: In a semiconductor integrated circuit device in which the number of the PMOS transistors to be used is relatively larger than that of the NMOS transistors and the PMOS transistor is used as an output driver, there is provided a semiconductor integrated circuit device having excellent stability, reliability, and performance while being inexpensive, and a manufacturing method thereof. In such a semiconductor integrated circuit device, complementary MOS circuits are composed of a P-type MOSFET (36) and an N-type MOSFET (37) which are a horizontal, an output driver is composed of a P-type vertical MOSFET (38) having a trench structure, and a conductivity type of the gate electrode of the respective MOSFETs is set as a P-type.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: January 18, 2005
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Publication number: 20040262677
    Abstract: A vertical MOS transistor achieving high reliability, and a method of manufacturing the vertical MOS transistor, are provided. Two types of trenches having different widths and depths are formed on the same substrate without increasing manufacturing process steps. The trenches are used differently, with a shallow trench having a narrow width mainly used as a driving transistor, and a wide, deep trench used as a countermeasure to degradation of long term reliability. Damage between a drain and a source is made to develop at the wide, deep trench, so as not to cause characteristics to degrade over the long term.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 30, 2004
    Inventor: Hirofumi Harada
  • Publication number: 20040209425
    Abstract: The invention provide a vertical MOS transistor which is capable of realizing high reliability, low cost and high yield through the transistor is miniature and has a high driving ability, and a method of manufacturing the same. Up to the middle of a trench is filled with a polycrystalline silicon gate electrode, and an intermediate insulating film is deposited so as to be filled in a remaining portion of the trench to flatten a main surface of a semiconductor substrate. The intermediate insulating film is etched back to expose the main surface of the semiconductor substrate over which a metal material is in turn deposited. Thus, the vertical MOS transistor can be formed without through a contact hole formation process. Since a layout margin for alignment deviation or the like is unnecessary, area saving is possible. Also, since the metal material is perfectly flattened, high reliability is obtained.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 21, 2004
    Inventor: Hirofumi Harada
  • Publication number: 20040188741
    Abstract: A vertical MOS transistor which is reduced in size and cost and which has high drive performance, reliability and yield is provided. Also provided is a method of manufacturing the vertical MOS transistor. A polycrystalline silicon gate electrode is buried halfway down a trench and an intermediate insulating film is put on top of the gate electrode to fill the rest of the trench. The intermediate insulating film then receives etch-back to form a metal electrode in a self-aligning manner without intervention of a contact hole. This eliminates the need to allow a layout margin for misalignment or the like and therefore makes it possible to reduce a transistor area. This also gives the transistor high reliability since the metal electrode is leveled thoroughly.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 30, 2004
    Inventor: Hirofumi Harada
  • Publication number: 20040124463
    Abstract: To provide a semiconductor integrated circuit device with a reduced noise at a low cost in a semiconductor integrated circuit composed of an MOSFET and adapted to operate, in particular, through DC drive or low-frequency drive. The semiconductor integrated circuit device is configured, in which a surface channel P-type MOSFET (101) and a buried channel N-type MOSFET (100) constitute a complementary MOS transistor with a P+ type gate electrode.
    Type: Application
    Filed: June 30, 2003
    Publication date: July 1, 2004
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6720633
    Abstract: A high withstand voltage insulated gate N-channel field effect transistor has N-type source and drain regions formed on a semiconductor substrate, and a channel forming region disposed between the source and drain regions. A gate insulating film is disposed over the channel forming region. A gate electrode is formed on the channel forming region through the gate insulating film. N-type low concentration regions are formed between respective ones of the drain region and the channel forming region and the source region and the channel forming region. Second insulating films are formed on respective ones of the low concentration regions. A P-type buried layer is formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source region, the drain region, the channel forming region, the gate insulating film, and the second insulating films. A P-type well layer is formed in a part of a region under the gate insulating film.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: April 13, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai
  • Patent number: 6710402
    Abstract: Disclosed are a vertical MOS transistor which lowers the gate resistance, improves the high frequency characteristics, and improves the yield compared with a conventional one and a method of manufacturing the same. When gate voltage is applied to a gate electrode, a channel is formed in a body region along a trench, and electrons or current flow(s) from a drain layer to a source layer. Here, a gate in the trench has a laminated structure of a polycrystalline silicon film and a metal silicide. Therefore, a gate resistance is lowered and the high frequency characteristics are improved. Further, according to the structure and the method of manufacturing, a concave portion generated at an upper portion of the gate in the trench when etching for forming the gate is less liable to be generated, and thus, malfunction and insufficient reliability due to the concave portion can be avoided.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: March 23, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Hirofumi Harada
  • Publication number: 20030228525
    Abstract: A process for prolonging the life of a lead-acid battery by adding an organic polymer and ultra fine lignin to its electrolyte and then charging the battery and the battery so produced.
    Type: Application
    Filed: May 15, 2003
    Publication date: December 11, 2003
    Inventors: Akiya Kozawa, Hirofumi Harada, Gijun Yokol
  • Publication number: 20030217103
    Abstract: An information storage input system for storing predetermined storage data in a storage server on a network accessible from a communication device open to public, includes a plurality of remote input terminal for inputting supplied input data in a predetermined input form, a remote input server for receiving input data from the remote input terminal, and a mobile communication terminal for communicating with at least the remote input server. Here, at least when the input data is stored in the storage server as the storage data, the remote input server notifies the fact to the mobile communication terminal.
    Type: Application
    Filed: November 26, 2002
    Publication date: November 20, 2003
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Hiroshi Yamamoto, Hiroshi Yamaguchi, Katsuo Shioiri, Hirofumi Harada, Keishi Higashi, Mitsuya Sato