Abstract: Provided is a semiconductor integrated circuit device capable of realizing an analog circuit required to have a high-precision relative ratio between adjacent transistors, which is reduced in size and cost. A single MOS transistor is provided within each of well regions. A plurality of the MOS transistors is combined to serve as an analog circuit block. Since distances between the well regions and channel regions may be made equal to one another, a high-precision semiconductor integrated circuit device can be obtained.

Abstract: A semiconductor device has a resistance circuit including a resistance element as a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film comprised of silicon nitride formed on the first thin film, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film, and a metal wiring formed on the contract hole. The first thin film has a low concentration impurity region and a high concentration impurity region at each of both ends of the low concentration impurity region. The second thin film is formed on the first thin film so as to be disposed on each of the high concentration impurity regions but not on the low concentration impurity region. An insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film.

Abstract: Provided is a method capable of forming a polycrystalline silicon resistor with preferable ratio accuracy so as to design a resistor circuit with high accuracy. In the method, a length of a low concentration impurity region constituting the polycrystalline silicon resistor in a longitudinal direction is varied in accordance with an occupying area of a metal portion overlapping the low concentration impurity region, thereby correcting a variation in resistance without varying an external shape and the occupying area of the resistor.

Abstract: In a method of manufacturing a semiconductor device, a barrier metal film and an aluminum metal film are formed on an insulating film on a semiconductor substrate. Two aluminum electrodes are formed in parallel with each other by patterning the barrier metal film and the aluminum metal film. The aluminum metal film in a region of part of each of the two aluminum electrodes are selectively removed to form two single-layer barrier metal electrodes separated from each other. A resistor is formed between the two single-layer barrier metal electrodes so as to electrically connect the two single-layer barrier metal electrodes to each other.

Abstract: Provided is a semiconductor integrated circuit device having flexible pin arrangement. A semiconductor integrated circuit is bonded to a die pad with an insulating paste, and the potential of the die pad is fixed through a bonding wire from an Al pad provided on the surface of the semiconductor integrated circuit. In the case of a P-type semiconductor substrate, the die pad is set as a terminal other than a terminal having a minimum operating potential of the semiconductor integrated circuit.

Abstract: Provided is a resistance circuit having a resistance element with high resistance and high accuracy. An insulating film such as a silicon nitride film is formed on the resistance element made of a thin film material whose thickness is reduced to 500 ? or smaller. The insulating film prevents passing through of the contact hole arranged on the resistance element during etching for forming the contact hole.

Abstract: Provided is a resistance element which is, when forming the resistance element including a resistor having a small thickness, less liable to cause disconnection of the resistor. Tip regions of electrodes which are formed by stacking a barrier metal film and an aluminum electrode film are formed so as to be single-layer barrier metal electrodes, and the resistor for electrically connecting the parallel barrier metal electrodes to each other is formed by lift-off.

Abstract: A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during a semiconductor manufacturing process is prevented from directly acting on the resistor, whereby resistance variation is suppressed.

Abstract: A structure of mounting a cowl top cover which has a back end portion mounted to a lower end portion of a front windshield panel. The structure includes: a surface portion disposed at the back end portion of cowl top cover, the surface portion covering a surface of lower end portion of front windshield panel and extending in a vehicular widthwise direction; a plurality of clip portions disposed at back end portion of cowl top cover, the lower end portion of front windshield panel being clamped between the clip portions and the surface portion in a plurality of places along the direction in which the surface portion extends; and a thin plate portion disposed at back end portion of cowl top cover, wherein the thin plate portion connecting plurality of clip portions with each other is thinner than surface portion and is spaced apart from front windshield panel.

Abstract: Provided is an improved depletion type MOS transistor for a semiconductor device, including: a first conductivity type well region on a semiconductor substrate; a gate insulating film formed on the well region; a gate electrode formed on the gate insulating film; second conductivity type source/drain regions formed on both sides of the gate electrode; a low concentration second conductivity type impurity region formed below the gate insulating film between the source/drain regions; and a low concentration first conductivity type impurity region formed below the low concentration second conductivity type impurity region between the source/drain regions.

Abstract: A structure of mounting a cowl top cover which has a back end portion mounted to a lower end portion of a front windshield panel is disclosed. The structure includes: a surface portion disposed at the back end portion of cowl top cover, the surface portion covering a surface of lower end portion of front windshield panel and extending in a vehicular widthwise direction; a plurality of clip portions disposed at back end portion of cowl top cover, the lower end portion of front windshield panel being clamped between the clip portions and the surface portion in a plurality of places along the direction in which the surface portion extends; and a thin plate portion disposed at back end portion of cowl top cover, wherein the thin plate portion connecting plurality of clip portions with each other is thinner than surface portion and is spaced apart from front windshield panel.

Abstract: Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high impurity concentration region, in which, the source/drain high impurity concentration region of the low-voltage NMOS transistor is doped with arsenic, while the source/drain high impurity concentration region of the high-voltage NMOS transistor is doped with phosphorus.

Abstract: Provided is a semiconductor integrated circuit device capable of realizing an analog circuit required to have a high-precision relative ratio between adjacent transistors, which is reduced in size and cost. A single MOS transistor is provided within each of well regions. A plurality of the MOS transistors is combined to serve as an analog circuit block. Since distances between the well regions and channel regions may be made equal to one another, a high-precision semiconductor integrated circuit device can be obtained.

Abstract: Provided is a semiconductor device including a depletion type MOS transistor and an enhancement type MOS transistor. In the semiconductor device, in order to provide a reference voltage generating circuit having an enhanced temperature characteristic or analog characteristic without increasing an area of the semiconductor device through addition of a circuit, well regions of the depletion type MOS transistor and the enhancement type MOS transistor, which have different concentrations from each other, are formed.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film disposed on the semiconductor substrate, and groups of resistors made of polycrystalline silicon and disposed on the first insulating film. At least some of the groups of resistors include at least one dummy resistor made of polycrystalline silicon. A second insulating film is disposed on the resistors and on the at least one dummy resistor of the resistor groups. First metal portions are disposed in respective contact holes disposed in the second insulating film for connecting respective portions of the resistors in the respective resistor groups. Second metal portions are disposed on the second insulating film and over the resistors and the at least one dummy resistor in the respective resistor groups.

Abstract: A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during a semiconductor manufacturing process is prevented from directly acting on the resistor, whereby resistance variation is suppressed.

Abstract: A semiconductor device has a first insulating film formed on a semiconductor substrate and resistors disposed on the first insulating film. Each of the resistors is formed of a polycrystalline silicon film having a low concentration impurity region and high concentration impurity regions disposed on opposite sides of the low concentration impurity region. The low concentration impurity regions of the plurality of resistors have different lengths from one another. A second insulating film is disposed on the resistors. Contact holes are formed on the second insulating film and are disposed on the high concentration impurity regions. First metal wirings are connected to the respective contact holes and connect the resistors in series. A second metal wiring is connected to one of the resistors located at one end of the resistors connected in series. The second metal wiring covers the low concentration impurity region of all of the resistors.

Abstract: In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a semiconductor substrate. A first insulating film is deposited over the main surface of the semiconductor substrate and the gate electrode, and the first insulating film is then etched to form side spacers made of the first insulating film on the wall surfaces of the trench so as to overly the gate electrode. A second insulating film is deposited over a main surface of the semiconductor substrate, the gate electrode, and the first insulating film. The second insulating film is then etched back so as to entirely expose the source region and the body contact region. A source metal electrode is formed over the main surface of the semiconductor substrate so as to cover the source region and body contact region.

Abstract: Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high impurity concentration region, in which, the source/drain high impurity concentration region of the low-voltage NMOS transistor is doped with arsenic, while the source/drain high impurity concentration region of the high-voltage NMOS transistor is doped with phosphorus.

Abstract: A high-reliable depletion-type MOS field-effect transistor as a process monitor is provided. A diode formed in polycrystalline silicon and a diode formed in a semiconductor substrate form a bi-directional diode. The bi-directional diode connects a gate electrode with the semiconductor substrate in the depletion-type MOS field-effect transistor through metal wirings.